feat: emit_verilog can emit the silicon-ready variant (clk_div) - #1889
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The capstone (full backprop trains XOR on live AX7203) ran on a hand-written board wrapper, not the CI-verified generator. emit_verilog / emit_verilog_deep now take clk_div (default 1 = unchanged). clk_div>1 emits the silicon-ready variant -- the exact fix that trains on silicon: register file forced to flip-flops (ram_style=registers, since distributed LUTRAM can't do the parallel weight init) + a /N clock-enable so the deep shared-core path gets ~clk_div*SETTLE cycles to settle (the open-source P&R can't express a multicycle constraint). clk_div only changes timing, not values -- verified bit-exact to the model in iverilog (clk_div=4, 12 training steps); default clk_div=1 is byte-identical to before, so the existing bit-exact/synth/datapath gate is unaffected. Self-test asserts the gating is emitted for clk_div=16 and absent for clk_div=1. The CI-verified generator now emits the same RTL that trains a neural net on real silicon. Refs #1764 Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
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…eady-clkdiv # Conflicts: # docs/NOW.md
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PR DashboardGenerated at: 2026-08-07 17:33:10 UTC
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The capstone (full backprop trains XOR on live AX7203) ran on a hand-written board wrapper, not the CI-verified generator. This closes the gap:
emit_verilog/emit_verilog_deepnow takeclk_div(default 1 = unchanged). clk_div>1 emits the silicon-ready variant — the exact fix that trains on silicon: register file forced to flip-flops (ram_style=registers, since distributed LUTRAM can't do the parallel weight init) + a /N clock-enable so the deep shared-core path gets ~clk_div×SETTLE cycles to settle (the open-source P&R can't express a multicycle constraint).clk_div only changes timing, not values — verified bit-exact to the model in iverilog (clk_div=4, 12 training steps, RTL == model); default clk_div=1 is byte-identical to before, so the existing bit-exact/synth/datapath gate is unaffected (still ALL SYNTHESIZE). Self-test asserts the gating is emitted for clk_div=16 and absent for clk_div=1. The CI-verified generator now emits the same RTL that trains a neural net on real silicon — unifying the verification and silicon threads. Refs #1764