docs: seed-lottery marginality is placement-level, Heisenbug-confirmed (Refs #1764) - #1896
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…r bug (Refs #1764) On-chip observability attempt (widen the UART dump to expose hidden pre-activations z0/z1 next to y) changed the design from marginally-computing to all-zero output: the added probe re-placed the shared core past its unconstrained timing edge. Documents this Heisenbug as positive evidence the seed-lottery fault is a timing/placement property of the whole deep path, not a localizable microcode step. Fix remains a real multicycle constraint (commercial P&R) / structural pipeline, not a code change. NOW.md updated. Refs #1764 Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
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Records a measured negative result from the on-silicon training work: an on-chip observability attempt (widening the UART result dump to expose the hidden pre-activations z0/z1 alongside the output y) flipped the design from marginally-computing to all-zero output. The added logic re-placed the shared core past its unconstrained timing edge — a genuine Heisenbug that is itself evidence the seed-lottery fault is a placement/timing property of the whole deep combinational path, not a localizable single-register bug. The remedy is a real multicycle timing constraint (commercial P&R) or a structural pipeline, not an RTL change.
Docs-only; no code or gate changes. Refs #1764