docs: pipeline prototype bit-exact, but dropped-in register won't cut depth -> go spec-level on_clock (Refs #1764) - #1904
Merged
Conversation
…t depth (Refs #1764) Variant 1 RTL prototype. Ruled out yosys auto-retiming (57->51, too weak). Built two 2-stage GftSmul prototypes (cut after product; cut mid-RNE), both bit-exact to the combinational core over ~40k random operands, but ltp rose 44->49/50: a register dropped into the generated combinational function defeats yosys cross-function optimization and the RNE/accumulator depth does not split there. Implication: the pipeline must be a spec-level on_clock where the compiler co-optimizes stages (multiply becomes a real pipelined primitive), not a hand-inserted register. Depth reduction is secondary anyway -- the untested lever is mid-cloud resync, and since the microsequencer waits settle >> 1 a latency-1 core needs no sequencer change. Added ruled-out items #8 (auto-retime) and #9 (dropped-in register). Refs #1764 Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
Contributor
Contributor
|
📓 NotebookLM Notebook linked to this PR
This notebook contains session context, decisions, and artifacts for this work. |
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
Starts Variant 1 (pipeline the shared core) with an RTL prototype and reports what it revealed.
synth_xilinx -retimemoves only a few levels (ltp 57 → 51 onGftSaddwith two output registers) — not enough to split the deep cloud.GftSmulprototypes, both bit-exact. Cut after the product, and cut mid-RNE (aftercarry/q/r); each verified bit-exact to the combinational core over ~40 k random operands. But ltp rose 44 → 49 / 50: dropping a register into the generated combinational function defeats yosys's cross-function optimization of the inlinedsadd/magmul/mul_noop, and the RNE-normalize/accumulator depth does not split at a hand-inserted register.on_clockwhere t27c co-optimizes the stages (and the multiply becomes a real pipelined primitive), not a register hand-dropped into codegen output. Added as ruled-out items [TASK-001]: Fix graph.tri — add missing spec declarations, fix typo #8 (auto-retime) and feat(ring-1): lex all 28 specs without errors [SEED-1] #9 (dropped-in register).settle≫ 1 cycle, a latency-1 pipelined core needs no sequencer change, so the decisive next experiment is to build the trainer on pipelined cores and see if the glitch dies.Prototypes in
scratchpad/retime/. Board untouched (generated capstone, XOR 4/4). Docs-only. Refs #1764