fix(gen-verilog): re-materialize test-block call temps after a rebinding - #1991
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A call-return temporary is CSE'd by call TEXT, but a test block mutates its bindings between statements (`st = on_ack(st);` repeated). Caching the temp across a reassignment reused a STALE value, so the modelled state never advanced -- every step re-tested the pre-mutation snapshot, and the divergence only showed on the Verilog path (Rust/Zig/C evaluate the calls directly). After any statement that rebinds a variable (StmtAssign, or a named StmtLocal), invalidate the materialized set so the next use re-assigns the temp from the current values. Nested-call temps inside a single non-mutating statement are unaffected -- they still materialize once, in dependency order. tri-net corpus: 6 runtime-divergence specs flip to passing (congestion_control, flow_control, network_simulator, production_scenarios, quarantine_manager, traffic_animator); full 99-spec icarus gate shows 0 regressions. FROZEN_HASH resealed. Refs #1948 Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
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Refs #1948 Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
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PR DashboardGenerated at: 2026-08-08 23:50:41 UTC
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Problem
A call-return temporary is CSE'd by call TEXT in the Verilog testbench, but a test block mutates its bindings between statements — the
st = on_ack(st);repeated-step pattern. Caching the temp across a reassignment reused a stale value, so the modelled state never advanced: every step re-tested the pre-mutation snapshot. The divergence only surfaced on the Verilog path (Rust/Zig/C evaluate the calls directly).Fix
After any statement that rebinds a variable (
StmtAssign, or a namedStmtLocal), invalidate the materialized set so the next use re-assigns the temp from the current values. Nested-call temps inside a single non-mutating statement are unaffected — they still materialize once, in dependency order (an earlier over-broad per-statement clear scrambled that; this is the narrow, mutation-scoped version).Validation
Refs #1948
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