FPGA Logic Networks Project: Stream Processing

Final project for the Logic Networks course at Polytechnic of Milan (Score: 28/30).

Solution Source (VHDL) | Technical Report

Overview

Designed and synthesized a hardware module in VHDL to process data streams from asynchronous RAM, compute dynamic confidence scores, and perform in-place memory mutations.

Key Achievements:

• Strict Timing: Exceeded the 20ns clock constraint, achieving a slack time of 16.204 ns.
• Zero Latches: Synthesized a strictly synchronous design utilizing 52 Flip-Flops and 0 Latches on an Artix-7 FPGA.
• Robust FSM: Implemented a 10-state FSM using a 3-process architecture (State Transition, Output, Registers) to isolate combinational logic from synchronous updates.
• Memory Interfacing: Handled protocol handshaking (i_start, o_done) and exact control signals for external memory read/write operations.

Architecture

The module processes sequential 8-bit words starting from a dynamic memory address. It imputes missing data (represented by 0x00) with the last known valid word, calculates a "credibility value" for each entry, and writes both back to precise memory offsets.

FSM Design

The control logic is driven by a 10-state FSM, separated into three concurrent VHDL processes:

1. state_transition: Combinational next-state decoding.
2. output: Memory operation timing and control buses (o_mem_en, o_mem_we).
3. registers: Synchronous data and address pointer updates on the clock's rising edge.

Synthesis Results

Target: Xilinx Artix-7 (xc7a200tfbg484-1) using Xilinx Vivado.

Metric	Result	Constraint
Flip-Flops	52	Minimize
Latches	0	0
Setup Slack	16.204 ns	$> 0$ (20ns clock)