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  • Fragment TEX instruction

    @digetx digetx committed Mar 19, 2017
    35bf184

  • Fragment "ALU:" prepend

    @digetx digetx committed Mar 19, 2017
    c200a37

  • Add missed MFU mul const 1.0 source register

    @digetx digetx committed Mar 19, 2017
    81b8fdd

  • Fragment MFU and linker syntax updates

    @digetx digetx committed Mar 18, 2017
    12d538b

  • Updated Fragment Shader ISA (markdown)

    @digetx digetx committed Mar 18, 2017
    bf52f42

  • Fragment z and w components

    @digetx digetx committed Mar 17, 2017
    8186ead

  • More on MFU MUL's

    @digetx digetx committed Mar 17, 2017
    003e0f3

  • Updated Assembler syntax (markdown)

    @digetx digetx committed Mar 17, 2017
    a5e99ea

  • Add some description for VEC4 select

    @digetx digetx committed Mar 14, 2017
    456940d

  • fix ALU "Addition disable" table formatting

    @digetx digetx committed Mar 14, 2017
    10b40ed

  • write pos.x and pos.y computations in similar order

    @kusma kusma committed Mar 14, 2017
    405af64

  • correct MFU varying source bit field

    @digetx digetx committed Mar 14, 2017
    b0fbaae

  • TEX instruction texcoord and destination registers bits

    @digetx digetx committed Feb 24, 2017
    865666e

  • Document "uniforms"

    @digetx digetx committed Feb 5, 2017
    698ba9f

  • try documenting some details about missing bits in MFU

    @kusma kusma committed Jan 18, 2017
    ed6783b

  • Enumerate the ALU "KILL" register

    @digetx digetx committed Jan 17, 2017
    98f2aa8

  • Linker assembler: reflect the fixed TRAM swizzle

    @digetx digetx committed Jan 17, 2017
    a55a995

  • Updated Shader Linking (markdown)

    @digetx digetx committed Jan 17, 2017
    0b3ad59

  • Fix TRAM destination swizzle

    @digetx digetx committed Jan 17, 2017
    66625a2

  • Updated Assembler syntax (markdown)

    @digetx digetx committed Jan 16, 2017
    e67a1cc

  • Updated Fragment Shader ISA (markdown)

    @digetx digetx committed Jan 16, 2017
    c5b1725

  • Updated Fragment Shader ISA (markdown)

    @digetx digetx committed Jan 16, 2017
    a15d110

  • Updated Assembler syntax (markdown)

    @digetx digetx committed Jan 16, 2017
    2e0bbc4

  • Updated Assembler syntax (markdown)

    @digetx digetx committed Jan 15, 2017
    bf11685

  • Updated Fragment Shader ISA (markdown)

    @digetx digetx committed Jan 15, 2017
    c839ba4

  • ALU position registers

    @digetx digetx committed Jan 15, 2017
    f5c80f4

  • Updated Assembler syntax (markdown)

    @digetx digetx committed Jan 15, 2017
    63f4d14

  • Updated Assembler syntax (markdown)

    @digetx digetx committed Jan 15, 2017
    b73e09e

  • MFU "var" syntax was changed

    @digetx digetx committed Jan 15, 2017
    e83796f

  • ALU "KILL" register

    @digetx digetx committed Jan 15, 2017
    df336a5