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[SYCL] PR 2 - Remove FPGA attributes from SYCL FE#21722

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againull merged 1 commit intointel:syclfrom
premanandrao:remote_fpga_pr2
Apr 10, 2026
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[SYCL] PR 2 - Remove FPGA attributes from SYCL FE#21722
againull merged 1 commit intointel:syclfrom
premanandrao:remote_fpga_pr2

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@premanandrao
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This removes the following attributes:

[[intel::loop_count(N)]]
[[intel::loop_count_avg(N)]]
[[intel::loop_count_min(N)]]
[[intel::loop_count_max(N)]]

This removes the following attributes:

[[intel::loop_count(N)]]
[[intel::loop_count_avg(N)]]
[[intel::loop_count_min(N)]]
[[intel::loop_count_max(N)]]
@premanandrao premanandrao requested a review from a team as a code owner April 9, 2026 22:25
@premanandrao
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#21102 requested that we split the large set of changes into manageable chunks.
Previous PR removing some FPGA loop attributes here: #21710

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@intel/llvm-gatekeepers please consider merging

@againull againull merged commit 7102583 into intel:sycl Apr 10, 2026
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3 participants