[SYCL] PR 3 - Remove FPGA attributes from SYCL FE#21735
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premanandrao wants to merge 3 commits intointel:syclfrom
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[SYCL] PR 3 - Remove FPGA attributes from SYCL FE#21735premanandrao wants to merge 3 commits intointel:syclfrom
premanandrao wants to merge 3 commits intointel:syclfrom
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This removes the following attributes: [[intel::ivdep]] [[intel::initiation_interval]] [[intel::ii]] [[intel::max_concurrency]] [[intel::speculated_iterations]] [[intel::max_reinvocation_delay]] [[intel::disable_loop_pipelining]] [[intel::enable_loop_pipelining]]
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This removes the following attributes:
[[intel::ivdep]]
[[intel::initiation_interval]]
[[intel::ii]]
[[intel::max_concurrency]]
[[intel::speculated_iterations]]
[[intel::max_reinvocation_delay]]
[[intel::disable_loop_pipelining]]
[[intel::enable_loop_pipelining]]