v0.1.0 — building blocks in MyHDL

The Python companion to libfpga. Seven verified FPGA building blocks written in MyHDL:

• sync_bit, reset_sync (CDC)
• fifo_sync (show-ahead FIFO with count)
• bin2gray / gray2bin, lfsr, mac

Every block simulates in pure Python with a self-checking pytest suite, and converts to clean Verilog and VHDL — CI compiles the generated Verilog with Icarus to prove it's real RTL, not just non-empty output.

pip install myhdl pytest && pytest

Try MyHDL in your browser: libfpga.com/learn/myhdl · intro: libfpga.com/blog/myhdl-intro

MIT · Copyright (c) 2026 Antonio Roldao, Ph.D.