v0.3.0 — co-simulation

The headline of this release is co-simulation: proof that the generated Verilog behaves identically to the MyHDL model.

Until now the library checked that each block simulates in Python and that it converts to compilable Verilog/VHDL. v0.3 adds the strongest guarantee: tests/test_cosim.py runs the converted Verilog through Icarus and drives it from the MyHDL testbench (via MyHDL's VPI bridge), asserting the real RTL matches the model on the same stimulus. If conversion ever introduced a semantic gap, this fails. Covers mac, lfsr, and arbiter_rr; CI builds the VPI (sources vendored) and asserts it can't silently skip.

New blocks:

• pulse_sync — single-cycle pulse across clock domains (toggle + 2-flop sync + edge detect)
• arbiter_rr — round-robin arbiter (one-hot grant, provably fair)

12 blocks total. The arbiter shipped with a conversion bug (mixed intbv/int on the priority pointer) that the conversion + cosim checks caught before release — exactly what they're for.

pip install myhdl pytest && pytest. MIT (vendored VPI sources are LGPL, see tests/cosim_vpi/NOTICE).

v0.2.0 — UART and SPI

Serial peripherals in MyHDL:

• uart_tx / uart_rx — 8N1 transmitter and receiver (mid-bit sampling, start-bit glitch rejection)
• spi_master — mode 0 (CPOL=0, CPHA=0), 8-bit, full duplex

Verified the way MyHDL makes elegant: the UART is tested by a transmitter-to-receiver loopback (send bytes into tx, read them out of rx, they must match), and the SPI master runs against a behavioral slave that checks what it received and echoes a known byte back. Both convert to Verilog and VHDL, and CI compiles the generated Verilog.

10 blocks total. pip install myhdl pytest && pytest.

MIT · libfpga.com/learn/myhdl

v0.1.0 — building blocks in MyHDL

The Python companion to libfpga. Seven verified FPGA building blocks written in MyHDL:

• sync_bit, reset_sync (CDC)
• fifo_sync (show-ahead FIFO with count)
• bin2gray / gray2bin, lfsr, mac

Every block simulates in pure Python with a self-checking pytest suite, and converts to clean Verilog and VHDL — CI compiles the generated Verilog with Icarus to prove it's real RTL, not just non-empty output.

pip install myhdl pytest && pytest

Try MyHDL in your browser: libfpga.com/learn/myhdl · intro: libfpga.com/blog/myhdl-intro

MIT · Copyright (c) 2026 Antonio Roldao, Ph.D.