v0.2.0 — UART and SPI

Serial peripherals in MyHDL:

• uart_tx / uart_rx — 8N1 transmitter and receiver (mid-bit sampling, start-bit glitch rejection)
• spi_master — mode 0 (CPOL=0, CPHA=0), 8-bit, full duplex

Verified the way MyHDL makes elegant: the UART is tested by a transmitter-to-receiver loopback (send bytes into tx, read them out of rx, they must match), and the SPI master runs against a behavioral slave that checks what it received and echoes a known byte back. Both convert to Verilog and VHDL, and CI compiles the generated Verilog.

10 blocks total. pip install myhdl pytest && pytest.

MIT · libfpga.com/learn/myhdl