The headline of this release is co-simulation: proof that the generated Verilog behaves identically to the MyHDL model.
Until now the library checked that each block simulates in Python and that it converts to compilable Verilog/VHDL. v0.3 adds the strongest guarantee: tests/test_cosim.py runs the converted Verilog through Icarus and drives it from the MyHDL testbench (via MyHDL's VPI bridge), asserting the real RTL matches the model on the same stimulus. If conversion ever introduced a semantic gap, this fails. Covers mac, lfsr, and arbiter_rr; CI builds the VPI (sources vendored) and asserts it can't silently skip.
New blocks:
pulse_sync— single-cycle pulse across clock domains (toggle + 2-flop sync + edge detect)arbiter_rr— round-robin arbiter (one-hot grant, provably fair)
12 blocks total. The arbiter shipped with a conversion bug (mixed intbv/int on the priority pointer) that the conversion + cosim checks caught before release — exactly what they're for.
pip install myhdl pytest && pytest. MIT (vendored VPI sources are LGPL, see tests/cosim_vpi/NOTICE).