firtool-1.142.0

What's Changed

• [Arc] Fix extraneous semicolons in TraceEncoder; NFC by @fabianschuiki in #9746
• [circt-bmc] Add LTLToCore to pipeline by @TaoBi22 in #9735
• [HW][circt-reduce] Add HW name sanitization by @seldridge in #9730
• Move ESI runtime tests into pytest suite by @teqdruid in #9655
• [CI] Cancel in-progress PR builds on new push by @Copilot in #9751
• [ImportVerilog][MooreToCore][Sim] Support queue element/range extractions in ImportVerilog and Sim by @Lauriethefish in #9727
• [Synth] Add resource usage analysis by @uenoku in #9717
• [HW] Make sure the index type for arrays is at least i1 by @pscabot in #9733
• [ImportVerilog] Make sampled value functions' results usable by Moore ops by @Arya-Golkari in #9718
• [ImportVerilog] Support $ literal within queue indexing expressions by @Lauriethefish in #9719
• [circt-reduce] Use per-port matching for FIRRTL port pruners by @seldridge in #9755
• [Arc] Add time operations for LLHD simulation support by @fabianschuiki in #9747
• [FIRRTL] Allow full reset module instances outside of reset domain by @fabianschuiki in #9754
• [HWToLLVM] Take the correct data layout alignment for alloca by @pscabot in #9734
• [FIRRTL][LowerToHW] Add InstanceChoiceOp lowering, Part 1 by @uenoku in #9742
• [FIRRTL] Fix domain info updates in cloneWithInsertedPorts by @seldridge in #9758
• [Datapath] Bug Fix for Sign-Extension Logic when Lowering Partial Products to Booth Arrays (#9726) by @cowardsa in #9744
• [ESI] Update test to exercise new functionality by @teqdruid in #9763
• [PyRTG] Add String format function by @maerhart in #9762
• [ESI][Runtime] Support editable installs by @teqdruid in #9764
• [ESI][Runtime] Improve support for extending pytest.cosim_test by @teqdruid in #9765
• [FIRRTL] Add instance macro attribute to InstanceChoice for Lowering by @uenoku in #9760
• [FIRRTL] Lazily construct CircuitNamespace, NFC by @uenoku in #9767
• [FIRRTL] Support FInstanceLike operations in ModuleInliner by @uenoku in #9688
• [ESI][Runtime] Don't crash on unsupported type by @teqdruid in #9768
• [PyCDE] Remove python 3.8, 3.9 and add 3.14 builds by @teqdruid in #9769
• [PyCDE] Disable cocotb tests by default by @teqdruid in #9770
• [Arc] Lower llhd.current_time to Arc in LowerState by @fabianschuiki in #9756
• [FIRRTL] Add domain create op by @seldridge in #9774
• [FIRRTL] Improve error messages for domain symbol verification by @seldridge in #9776
• [Moore][ImportVerilog] Add support for fork-join blocks by @tdps2 in #9682
• [FIRRTL] Add conservative IMDCE handling for InstanceChoiceOp by @uenoku in #9710
• [Arc] Lower time operations to LLVM IR by @fabianschuiki in #9757
• [FIRRTL] Support merging layers in LinkCircuits by @unlsycn in #9677
• [ImportVerilog] Add support for $swrite by @fabianschuiki in #9782
• [Moore] Add %m/%M hierarchical path format specifier by @fabianschuiki in #9783
• [Comb] [NFC] Reorder arguments for the consistency in CombOps create* helpers by @uenoku in #9799
• [RTG] Same seed for all tests & random scopes by @maerhart in #9793
• [RTG][Elaboration] Fix getUniformInRange by @maerhart in #9806
• [PyCDE] Fix Struct metaclass for Python 3.14 (PEP 649/749 annotations) and CI disk space by @Copilot in #9773
• [circt-verilog] Bump slang version requirement to 10.0 by @unlsycn in #9808
• [ImportVerilog][Sim][MooreToCore] Add support for resizing queues by @Lauriethefish in #9780
• [Arc] Use simulation time for VCD timestamps by @fabianschuiki in #9785
• [Moore][MooreToCore][Sim] Support for basic uses of moore.dyn_queue_ref_element by @Lauriethefish in #9778
• [ImportVerilog][Moore] Add support for queue concatenations by @Lauriethefish in #9777
• [ESI Runtime] Add statically typed port wrappers by @teqdruid in #9771
• [ESI] Add ValidOnly channel signaling protocol by @teqdruid in #9787
• [ESI][Copilot] Add ESI runtime development skills file by @teqdruid in #9812
• [Comb] Officialize support for zero-width integers by @Moxinilian in #6959
• [SV] Add an utility function to construct nested ifdefs by @uenoku in #9798
• [FIRRTL] Allow keywords as identifiers in expressions by @seldridge in #9788
• [ImportLiberty] Remove unused functions, NFC by @uenoku in #9813
• [FIRRTL] Add case_macro attribute to OptionCaseOp and refactor PopulateInstanceChoiceSymbols by @uenoku in #9797
• [FIRRTL][LowerToHW] Require instance_macro before lowering by @uenoku in #9814
• [FIRRTL] Allow Unknown as an identifier by @seldridge in #9789
• [RTG][circt-tblgen] Add RegisterAllocationOpInterface methods and decorators by @maerhart in #9801
• [VerifToSMT] Add meaningful name prefixes to BMC symbolic constants by @5iri in #9794
• [ImportVerilog] Add support for associative array extractions by @Elijah-Cheesman in #9796
• [HWToBTOR2][NFC] Fix typo in multi-clock error by @TaoBi22 in #9819
• [Synth][CutRewriter] Add LogicNetwork flat IR by @uenoku in #9804
• [Synth][CutRewriter] Migrate CutRewriter to use Flat IR by @uenoku in #9805
• [ESI][Cosim][Pytest] Increase debug-ability of cosim pytest runs by @teqdruid in #9825
• [Tools] Set bug report messages to CIRCT by @uenoku in #9826
• [Synth][CutRewriter] Add a LEC test for mig/xor, NFC by @uenoku in #9828
• [FSM] Convert FSM to SMT by @luisacicolini in #9379
• [FIRRTL][Inliner] Fix NLA updates during flattening by @seldridge in #9810
• [ImportVerilog] Add delete and clear ops for assoc arrays by @Elijah-Cheesman in #9823
• [FIRRTL][Inliner] Remove flattenPoint, use inlinedSymbols by @seldridge in #9816
• [RTG][circt-tblgen] Auto-generate instruction assembly and binary emission methods by @maerhart in #9802
• [ImportVerilog] Support DPI-C extern declarations and open arrays by @pscabot in #9809
• [FIRRTL] InstanceChoice support for LowerToHW, Part 2(ABI lowering) by @uenoku in #9761
• [FIRRTL][LowerDomains] Add support for DomainCreateOp by @seldridge in #9781
• [Synth][CutRewriter] Fix potential non-determinism by @uenoku in #9830
• [LowerToHW] Use "-" for instance choice header file delimiter by @uenoku in #9832
• [Synth][SOPBalancing] Fix non-determinism from duplicated value numbering by @uenoku in #9836
• [FIRRTL] Use hw.hierpath in CreateSiFiveMetadata by @seldridge in #9829
• [HWToBTOR2] Strengthen multi-clocking detection by @TaoBi22 in #9820
• Update to avoid arith i0 by @jpienaar in #9835
• [ImportVerilog] Waive another valgrind test, NFC by @seldridge in #9841
• [Handshake] Fix deprecated builder.create warnings by @seldridge in #9843
• [SV] Remove extract-test-code by @rwy7 in #8846

New Contributors

• @tdps2 made their first contribution in #9682
• @Elijah-Cheesman made their first contribution in #9796

Full Changelog: firtool-1.141.0...firtool-1.142.0