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firtool-1.152.0

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@seldridge seldridge released this 04 Jul 04:21
firtool-1.152.0
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seldridge Schuyler Eldridge
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Learn about vigilant mode.
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Learn about vigilant mode.

What's Changed

  • [ImportVerilog][Moore] Add $fscanf/$sscanf and scan format support by @VecoMr in #10605
  • [ImportVerilog][Moore][Sim] Add $timeformat system task support by @VecoMr in #10614
  • [Moore][Sim] Add %l/%L library binding format specifier by @VecoMr in #10716
  • [Arc] Add LowerProcesses pass by @fabianschuiki in #10740
  • [FIRRTL][Dedup] Reuse NLA in addAnnotationContext for singly instantiated module by @uenoku in #10731
  • [FIRRTL][Inliner] Only local-ize NLA's rooted in that module. by @dtzSiFive in #10651
  • [Support] Add noWrap option to PrettyPrinter by @TaoBi22 in #10748
  • [MooreToCore] Fix bool cast lowering for $time by @VecoMr in #10758
  • [circt-synth] Use correct reqires in integration test by @maerhart in #10759
  • [ImportVerilog] Support field width on %s format specifiers by @micprog in #10749
  • [FIRRTL][Inliner] Make setInnerSym idempotent for same-sym re-rename by @dtzSiFive in #10752
  • [FIRRTL][Inliner] Handle single-element hierpath in writeback by @dtzSiFive in #10753
  • [FIRRTL][Inliner] Fix hasRoot, drop rootSet, fix crash. by @dtzSiFive in #10762
  • [MooreToCore][Sim][SimToSV] Add string comparison lowering by @VecoMr in #10766
  • [FIRRTL] unsafe_domain_cast in InferResets by @seldridge in #10768

Full Changelog: firtool-1.151.0...firtool-1.152.0

Contributors

fabianschuiki, seldridge, and 6 other contributors
Assets 26
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