·
12 commits
to main
since this release
What's Changed
- [ESI][Cosim] Link lz4 for Verilator FST tracing builds by @teqdruid in #10998
- [ESI][Cosim] Raise the stack limit before running verilator_bin by @teqdruid in #10999
- [ESI][Cosim] Prefer clang and lld for building the verilated model by @teqdruid in #11000
- [ci] Drop -large runners in UBTI workflow_dispatch by @seldridge in #11006
- [MooreToCore] Fix out-of-bounds and aggregate moore.extract lowering by @fzi-haxel in #10993
- [ci] Don't build/test Python on macos-*-intel by @seldridge in #11007
- [FIRRTL] Add register 'initial' time-zero value attribute by @prithayan in #10949
- [ESI][Cosim] Compile cold-path and runtime code at lower optimization by @teqdruid in #11001
- [PyCDE] Add seq.DownCounter, fix Counter clear/increment priority by @teqdruid in #11010
- [ESI][Cosim] Skip the cmake configure step when nothing changed by @teqdruid in #11002
- [ESI][Cosim] Tune --output-split for the C++ build by @teqdruid in #11003
- [OM] Remove evaluator worklist and reference values by @uenoku in #10928
- [FIRRTL][Inliner] Prune redundant paths during the upward trace by @dtzSiFive in #10968
- [NFC][Inliner] Add ascii graph visualizer to test, thanks! by @dtzSiFive in #11017
- [PyCDE][ESI] Count down for list-window burst counters by @teqdruid in #11011
- [docs] Add terse Style Guide by @seldridge in #11019
- [PyCDE][ESI] Add ChannelMergeOneValid by @teqdruid in #11012
- Bump LLVM to 95bde4372e3f98a60da6f98f2bc29d435e9cef70 by @trmckay in #11020
- [LLHD] Make llhd-inline-calls best-effort on recursion by @fabianschuiki in #11023
- llvm: fix submodule by @trmckay in #11031
- [circt-bmc][circt-lec][arcilator] Register codegen passes before JIT by @Clo91eaf in #11009
- [HWAggregateToComb] Lower
hw.array_sliceto comb dialect by @rocallahan in #11021 - [Datapath] Detecting Repeated Extension Bits to Simplify Compress Operations by @cowardsa in #10992
- [circt-hm] Add a rationale for circt-hm by @rwy7 in #11016
- [Moore] Remove moore.conversion op by @fabianschuiki in #11024
- [ImportVerilog] Reject inout ports with mismatched types by @fabianschuiki in #11029
- [OM] Fix untracked op mutation by @uenoku in #11034
- [CIRCT] XFAIL tests with expensive pattern checks by @uenoku in #11035
- [circt-synth] Detect Signed Squarer by @cowardsa in #11038
- [FIRRTL] Remove old full-reset flow and MemToReg pass by @uenoku in #10943
- Bump LLVM to pickup temporary revert of 2-3x slowdown. by @dtzSiFive in #11040
Full Changelog: firtool-1.156.0...firtool-1.157.0