firtool-1.162.0

What's Changed

• [PyCDE] Add If construct with callable branches by @teqdruid in #11212
• [ExportVerilog] Change hw.union padding to match bitcast layout by @fzi-hielscher in #11135
• [ExportVerilog] Add sv.var declaration support by @okekayode in #11209
• [HWArithToHW] Convert aggregate constant field attributes by @teqdruid in #11217
• [HW] Allow hw.constant to produce type aliases of integers by @teqdruid in #11196
• [circt-verilog] Infer clock ports from clock uses by @prithayan in #11175
• [SV] Enforce packed type boundaries for nets by @okekayode in #11215
• [Docs][ExportVerilog] Document svVarDeclStyle lowering option by @okekayode in #11218
• [HWArith] Allow hwarith.constant to produce type aliases of integers by @teqdruid in #11197
• [PyCDE] Raise an error when creating signals outside a generator by @teqdruid in #11198
• [SV] Add externally defined packages via sv.package.extern by @teqdruid in #11207
• [PyCDE] Support importing externally provided packages by @teqdruid in #11204
• [PyCDE] Unwrap typedefs before integer operations by @teqdruid in #11227
• [ESI][Runtime] Match corrected hw.union alignment by @teqdruid in #11226
• [PyCDE] Add changelog for 0.12.0 by @teqdruid in #11229
• PyCDE: Add a PyPI package description by @teqdruid in #11230
• [PyCDE] Normalize array selectors without changing their width by @teqdruid in #11228
• [ESI][Runtime] Add package description and 0.8.0 changelog by @teqdruid in #11231
• [FIRRTL] Separate domain stripping from inference by @uenoku in #11211
• [SV] Enforce type boundaries for vars by @okekayode in #11224
• [ESI] Bump ABI version and reject incompatible manifests by @teqdruid in #11225
• [ExportVerilog] Do not emit "logic" before typedef, enum and union types by @vpalatin in #11178
• [Sim] Add !sim.variant type by @fzi-hielscher in #11193
• Update PyCDE version requirement in CHANGELOG by @teqdruid in #11237
• [HW][Sim][Support] Move aggregate FieldInfo to Support library by @fzi-hielscher in #11235
• [AXI4] Verify port windows fit in the address width by @TaoBi22 in #11222
• [LLHD] Preserve explicit register initializers through Deseq by @5iri in #11081
• [PIR] Introduce the SVA interfacing pir dialect by @dobios in #11180
• [Moore] Fix SVModuleOp::print to print attributes before body region. by @SimonEbner in #11245
• [ImportVerilog] Support module-level SV attributes. by @SimonEbner in #11244
• [HW] Remove generic InOut port direction support by @okekayode in #11232
• Add svVarDeclStyle to --lowering-options help text by @okekayode in #11252
• [ESI][BSP] Allow custom ChannelService implementations in CosimBSP by @teqdruid in #11254
• [HW][SV] Derive port kind from type by @okekayode in #11249
• [FIRRTL] Reject domain values in aggregates by @uenoku in #11255
• [FIRRTL] Add bitwise operations for integer properties by @arhum04 in #11257
• [ESI][Runtime] Let SegmentedMessageData hand HostMem regions to backends by @teqdruid in #11253
• Anticipate upstream addition of MapVector to MLIRSupport. by @ingomueller-net in #11263
• [Comb] Fix computeKnownBits for comb.shl and comb.shru overshift. by @dma14 in #11259
• [ExportVerilog][NFC] Derive port name alignment from the emitted prefixes by @okekayode in #11265
• Bump LLVM by @uenoku in #11096
• [NFC] Fix deprecation warnings related to aggregate builders by @uenoku in #11277
• [Arc] Remove DenseMapInfo specialization for SmallVector<Value>, NFC by @fzi-hielscher in #11278
• [FIRRTL] Support setting instance name in hierarcy injection by @jackkoenig in #11279
• [FIRRTL] Misc aggregate fold fixes by @tynan-jdwk in #11250
• [ProbeToSV] Lower probe.send/probe.read to SV by @nanjo712 in #11077
• [SV] Fix dangling Properties in InterfaceInstanceOp builder by @dtzSiFive in #11281
• Drop using namespace llvm from several files, NFC by @fzi-hielscher in #11280
• [ESI][Runtime] Expose HostMem.start() to Python by @teqdruid in #11283
• [OM] Support arbitrary precision integer bitwise properties by @arhum04 in #11258
• [ESI][BSP] Support multiple outstanding reads in HostMemReadReqSplitter by @teqdruid in #11282
• [RTG] Destroy instruction format AST nodes before freeing the arena by @youngar in #11266
• [LLHD][Deseq] Infer register preset value from concurrent drives by @fzi-hielscher in #11260
• Support combinational user-defined primitives (UDPs) in circt::ImportVerilog by @qiaozhang-pr in #11238
• [OM] Don't assume the ClassFieldsOp has a FusedLoc with metadata. by @mikeurbach in #11219
• [FIRRTL] Only narrow signed subtraction in SubOfPad canonicalizers by @vera-rubin in #11290
• [ExportVerilog] Add emitPortType lowering option by @okekayode in #11262
• [circt-test] Add instrumentation and various performance improvements by @uenoku in #11295

New Contributors

• @vpalatin made their first contribution in #11178
• @arhum04 made their first contribution in #11257
• @dma14 made their first contribution in #11259
• @tynan-jdwk made their first contribution in #11250
• @qiaozhang-pr made their first contribution in #11238
• @vera-rubin made their first contribution in #11290

Full Changelog: firtool-1.161.0...firtool-1.162.0