[AMDGPU] Avoid undefs in hazard-gfx1250-flat-scr-hi.mir. NFC #170396

rampitec · 2025-12-03T00:37:34Z

No description provided.

rampitec · 2025-12-03T00:37:35Z

[AMDGPU] Avoid undefs in hazard-gfx1250-flat-scr-hi.mir. NFC #170396 👈
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This stack of pull requests is managed by sgh.

llvmbot · 2025-12-03T00:39:28Z

@llvm/pr-subscribers-backend-amdgpu

Author: Stanislav Mekhanoshin (rampitec)

Changes

Full diff: https://github.com/llvm/llvm-project/pull/170396.diff

1 Files Affected:

(modified) llvm/test/CodeGen/AMDGPU/hazard-gfx1250-flat-scr-hi.mir (+54-30)

diff --git a/llvm/test/CodeGen/AMDGPU/hazard-gfx1250-flat-scr-hi.mir b/llvm/test/CodeGen/AMDGPU/hazard-gfx1250-flat-scr-hi.mir
index e3b28c5518695..5dafa1b72ed10 100644
--- a/llvm/test/CodeGen/AMDGPU/hazard-gfx1250-flat-scr-hi.mir
+++ b/llvm/test/CodeGen/AMDGPU/hazard-gfx1250-flat-scr-hi.mir
@@ -8,10 +8,12 @@ body:             |
   bb.0:
 
     ; GCN-LABEL: name: s_ashr_i64
-    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi
-    ; GCN-NEXT: [[S_ASHR_I64_:%[0-9]+]]:sreg_64 = S_ASHR_I64 undef %2:sreg_64, [[COPY]], implicit-def $scc
+    ; GCN: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
+    ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi
+    ; GCN-NEXT: [[S_ASHR_I64_:%[0-9]+]]:sreg_64 = S_ASHR_I64 [[DEF]], [[COPY]], implicit-def $scc
+    %1:sreg_64 = IMPLICIT_DEF
     %0:sreg_32 = COPY $src_flat_scratch_base_hi
-    %2:sreg_64 = S_ASHR_I64 undef %1:sreg_64, %0, implicit-def $scc
+    %2:sreg_64 = S_ASHR_I64 %1:sreg_64, %0, implicit-def $scc
 ...
 
 ---
@@ -21,10 +23,12 @@ body:             |
   bb.0:
 
     ; GCN-LABEL: name: s_lshl_b64
-    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi
-    ; GCN-NEXT: [[S_LSHL_B64_:%[0-9]+]]:sreg_64 = S_LSHL_B64 undef %2:sreg_64, [[COPY]], implicit-def $scc
+    ; GCN: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
+    ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi
+    ; GCN-NEXT: [[S_LSHL_B64_:%[0-9]+]]:sreg_64 = S_LSHL_B64 [[DEF]], [[COPY]], implicit-def $scc
+    %1:sreg_64 = IMPLICIT_DEF
     %0:sreg_32 = COPY $src_flat_scratch_base_hi
-    %2:sreg_64 = S_LSHL_B64 undef %1:sreg_64, %0, implicit-def $scc
+    %2:sreg_64 = S_LSHL_B64 %1:sreg_64, %0, implicit-def $scc
 ...
 
 ---
@@ -34,10 +38,12 @@ body:             |
   bb.0:
 
     ; GCN-LABEL: name: s_lshr_b64
-    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi
-    ; GCN-NEXT: [[S_LSHR_B64_:%[0-9]+]]:sreg_64 = S_LSHR_B64 undef %2:sreg_64, [[COPY]], implicit-def $scc
+    ; GCN: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
+    ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi
+    ; GCN-NEXT: [[S_LSHR_B64_:%[0-9]+]]:sreg_64 = S_LSHR_B64 [[DEF]], [[COPY]], implicit-def $scc
+    %1:sreg_64 = IMPLICIT_DEF
     %0:sreg_32 = COPY $src_flat_scratch_base_hi
-    %2:sreg_64 = S_LSHR_B64 undef %1:sreg_64, %0, implicit-def $scc
+    %2:sreg_64 = S_LSHR_B64 %1:sreg_64, %0, implicit-def $scc
 ...
 
 ---
@@ -47,10 +53,12 @@ body:             |
   bb.0:
 
     ; GCN-LABEL: name: s_bfe_i64
-    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi
-    ; GCN-NEXT: [[S_BFE_I64_:%[0-9]+]]:sreg_64 = S_BFE_I64 undef %2:sreg_64, [[COPY]], implicit-def $scc
+    ; GCN: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
+    ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi
+    ; GCN-NEXT: [[S_BFE_I64_:%[0-9]+]]:sreg_64 = S_BFE_I64 [[DEF]], [[COPY]], implicit-def $scc
+    %1:sreg_64 = IMPLICIT_DEF
     %0:sreg_32 = COPY $src_flat_scratch_base_hi
-    %2:sreg_64 = S_BFE_I64 undef %1:sreg_64, %0, implicit-def $scc
+    %2:sreg_64 = S_BFE_I64 %1:sreg_64, %0, implicit-def $scc
 ...
 
 ---
@@ -60,10 +68,12 @@ body:             |
   bb.0:
 
     ; GCN-LABEL: name: s_bfe_u64
-    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi
-    ; GCN-NEXT: [[S_BFE_U64_:%[0-9]+]]:sreg_64 = S_BFE_U64 undef %2:sreg_64, [[COPY]], implicit-def $scc
+    ; GCN: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
+    ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi
+    ; GCN-NEXT: [[S_BFE_U64_:%[0-9]+]]:sreg_64 = S_BFE_U64 [[DEF]], [[COPY]], implicit-def $scc
+    %1:sreg_64 = IMPLICIT_DEF
     %0:sreg_32 = COPY $src_flat_scratch_base_hi
-    %2:sreg_64 = S_BFE_U64 undef %1:sreg_64, %0, implicit-def $scc
+    %2:sreg_64 = S_BFE_U64 %1:sreg_64, %0, implicit-def $scc
 ...
 
 ---
@@ -86,10 +96,14 @@ body:             |
   bb.0:
 
     ; GCN-LABEL: name: s_bitcmp0_b64
-    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi
-    ; GCN-NEXT: S_BITCMP0_B64 undef %1:sreg_64, [[COPY]], implicit undef $scc, implicit-def $scc
+    ; GCN: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
+    ; GCN-NEXT: $scc = IMPLICIT_DEF
+    ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi
+    ; GCN-NEXT: S_BITCMP0_B64 [[DEF]], [[COPY]], implicit $scc, implicit-def $scc
+    %1:sreg_64 = IMPLICIT_DEF
+    $scc = IMPLICIT_DEF
     %0:sreg_32 = COPY $src_flat_scratch_base_hi
-    S_BITCMP0_B64 undef %1:sreg_64, %0, implicit undef $scc, implicit-def $scc
+    S_BITCMP0_B64 %1:sreg_64, %0, implicit $scc, implicit-def $scc
 ...
 
 ---
@@ -99,10 +113,14 @@ body:             |
   bb.0:
 
     ; GCN-LABEL: name: s_bitcmp1_b64
-    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi
-    ; GCN-NEXT: S_BITCMP1_B64 undef %1:sreg_64, [[COPY]], implicit undef $scc, implicit-def $scc
+    ; GCN: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
+    ; GCN-NEXT: $scc = IMPLICIT_DEF
+    ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi
+    ; GCN-NEXT: S_BITCMP1_B64 [[DEF]], [[COPY]], implicit $scc, implicit-def $scc
+    %1:sreg_64 = IMPLICIT_DEF
+    $scc = IMPLICIT_DEF
     %0:sreg_32 = COPY $src_flat_scratch_base_hi
-    S_BITCMP1_B64 undef %1:sreg_64, %0, implicit undef $scc, implicit-def $scc
+    S_BITCMP1_B64 %1:sreg_64, %0, implicit $scc, implicit-def $scc
 ...
 
 ---
@@ -125,10 +143,12 @@ body:             |
   bb.0:
 
     ; GCN-LABEL: name: s_bitset0_b64
-    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi
-    ; GCN-NEXT: [[S_BITSET0_B64_:%[0-9]+]]:sreg_64 = S_BITSET0_B64 [[COPY]], undef [[S_BITSET0_B64_]], implicit-def $scc
+    ; GCN: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
+    ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi
+    ; GCN-NEXT: [[DEF:%[0-9]+]]:sreg_64 = S_BITSET0_B64 [[COPY]], [[DEF]], implicit-def $scc
+    %1:sreg_64 = IMPLICIT_DEF
     %0:sreg_32 = COPY $src_flat_scratch_base_hi
-    %1:sreg_64 = S_BITSET0_B64 %0, undef %1:sreg_64, implicit-def $scc
+    %1:sreg_64 = S_BITSET0_B64 %0, %1:sreg_64, implicit-def $scc
 ...
 
 ---
@@ -138,10 +158,12 @@ body:             |
   bb.0:
 
     ; GCN-LABEL: name: s_bitset1_b64
-    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi
-    ; GCN-NEXT: [[S_BITSET1_B64_:%[0-9]+]]:sreg_64 = S_BITSET1_B64 [[COPY]], undef [[S_BITSET1_B64_]], implicit-def $scc
+    ; GCN: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
+    ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi
+    ; GCN-NEXT: [[DEF:%[0-9]+]]:sreg_64 = S_BITSET1_B64 [[COPY]], [[DEF]], implicit-def $scc
+    %1:sreg_64 = IMPLICIT_DEF
     %0:sreg_32 = COPY $src_flat_scratch_base_hi
-    %1:sreg_64 = S_BITSET1_B64 %0, undef %1:sreg_64, implicit-def $scc
+    %1:sreg_64 = S_BITSET1_B64 %0, %1:sreg_64, implicit-def $scc
 ...
 
 ---
@@ -151,8 +173,10 @@ body:             |
   bb.0:
 
     ; GCN-LABEL: name: s_ashr_i64_phys_dst
-    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi
-    ; GCN-NEXT: $sgpr0_sgpr1 = S_ASHR_I64 undef %1:sreg_64, [[COPY]], implicit-def $scc
+    ; GCN: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
+    ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi
+    ; GCN-NEXT: $sgpr0_sgpr1 = S_ASHR_I64 [[DEF]], [[COPY]], implicit-def $scc
+    %1:sreg_64 = IMPLICIT_DEF
     %0:sreg_32 = COPY $src_flat_scratch_base_hi
-    $sgpr0_sgpr1 = S_ASHR_I64 undef %1:sreg_64, %0, implicit-def $scc
+    $sgpr0_sgpr1 = S_ASHR_I64 %1:sreg_64, %0, implicit-def $scc
 ...

github-actions · 2025-12-03T01:24:05Z

🐧 Linux x64 Test Results

186884 tests passed
4920 tests skipped

✅ The build succeeded and all tests passed.

…-flat-scr-hi.mir

rampitec mentioned this pull request Dec 3, 2025

[AMDGPU] Handle phys regs in flat_scratch_base_hi operand check #170395

Merged

rampitec requested a review from arsenm December 3, 2025 00:38

rampitec marked this pull request as ready for review December 3, 2025 00:38

llvmbot added the backend:AMDGPU label Dec 3, 2025

rampitec mentioned this pull request Dec 3, 2025

[AMDGPU] Prevent folding of flat_scr_base_hi into a 64-bit SALU #170373

Merged

arsenm approved these changes Dec 3, 2025

View reviewed changes

Base automatically changed from users/rampitec/handle-physreg-in-flat-scr-hi-check to main December 3, 2025 01:22

rampitec force-pushed the users/rampitec/avoid-undef-in-hazard-gfx1250-flat-scr-hi.mir branch from 78f3a2a to 679a004 Compare December 3, 2025 01:28

[AMDGPU] Avoid undefs in hazard-gfx1250-flat-scr-hi.mir. NFC

ca750bd

rampitec force-pushed the users/rampitec/avoid-undef-in-hazard-gfx1250-flat-scr-hi.mir branch from 679a004 to ca750bd Compare December 3, 2025 01:53

Merge branch 'main' into users/rampitec/avoid-undef-in-hazard-gfx1250…

08ed95a

…-flat-scr-hi.mir

rampitec merged commit befa4e8 into main Dec 3, 2025
10 checks passed

rampitec deleted the users/rampitec/avoid-undef-in-hazard-gfx1250-flat-scr-hi.mir branch December 3, 2025 08:14

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[AMDGPU] Avoid undefs in hazard-gfx1250-flat-scr-hi.mir. NFC #170396

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[AMDGPU] Avoid undefs in hazard-gfx1250-flat-scr-hi.mir. NFC #170396

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