Writing to TX buffer while TX is ongoing is illegal and behaviour is not defined. Nonetheless there is a test case for this - the test doesn't specify the expected behaviour, but it tests that the DUT is not broken afterwards and will behave correctly for subsequent packets.
Because OpenTitan/Mocha's prim_assert.sv disables assertions for Verilator, this test always passes.
If you manually enable assertions, the test occasionally fails.
This is because there is an AXI Stream driven by the TX buffer read output. AXI Streams are forbidden from changing their data while tvalid && !tready, but the data will change if a write occurs to the buffer supplying that data. This is relatively rare.
This is a test issue, not a design issue. We need a way of disabling certain assertions for certain tests.
Writing to TX buffer while TX is ongoing is illegal and behaviour is not defined. Nonetheless there is a test case for this - the test doesn't specify the expected behaviour, but it tests that the DUT is not broken afterwards and will behave correctly for subsequent packets.
Because OpenTitan/Mocha's
prim_assert.svdisables assertions for Verilator, this test always passes.If you manually enable assertions, the test occasionally fails.
This is because there is an AXI Stream driven by the TX buffer read output. AXI Streams are forbidden from changing their data while
tvalid && !tready, but the data will change if a write occurs to the buffer supplying that data. This is relatively rare.This is a test issue, not a design issue. We need a way of disabling certain assertions for certain tests.