20250129_01

Update EC commit, bugfix for old issue

It turns out that HyperDebug firmware never used the fully correct
procedure for switching to fast clock frequency, failing to wait for
core power rail to stabilize at higher voltage, before switching the
clock source.

This resulted in undefined behavior on startup.  By accident/chance we
have not seen any advese effects until the last batch of changes, which
seems to randomly have triggered an isue.

765b8a9d2b chip/stm32: Wait for core voltage to stabilize on STM32L4/5