Build OpenSBI#403
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Those specific linker warnings seem to be caused by empty declared arrays (as I disabled support for platforms other than ours to shrink the binaries and improve boot speed). I don't think there is much that can be done about them (they appear in CHERI Linux too). |
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Marking this as draft because it is marked as work in progress. |
marnovandermaas
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This is really exciting! I just have a few nits. It's probably best to merge the PR to move the Boot ROM into the ROM before doing this PR as there is some overlap in changes.
| uint32_t boot_addr = 0; | ||
| while (!get_boot_addr(&boot_addr)) { | ||
| uprintf(boot_ctx.console, "Entering SPI bootstrap\n"); | ||
| // Spin polling the spi_dev and processing incoming data until a reset command is received. | ||
| spi_boot_strap(&boot_ctx); | ||
| uint32_t boot_addr; | ||
| if (!get_boot_addr(&boot_addr)) { | ||
| uprintf(boot_ctx.console, "No valid slot found, default to DRAM\n"); | ||
| boot_addr = dram_base; | ||
| } |
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Probably best to merge Douglas's PR first which fixes this by clearing the slots first.
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The boot slot clearing is needed for successive tests, but this is also needed independently because modifying OpenSBI/any next stage software to include the magic is a quite intrusive change to upstream software (I also couldn't get that to work for some reason).
Signed-off-by: Alice Ziuziakowska <a.ziuziakowska@lowrisc.org>
Signed-off-by: Alice Ziuziakowska <a.ziuziakowska@lowrisc.org>
adding devicetree data makes the ROM too big to fit in 0x4000 bytes, so bump this up for now. Signed-off-by: Alice Ziuziakowska <a.ziuziakowska@lowrisc.org>
Signed-off-by: Alice Ziuziakowska <a.ziuziakowska@lowrisc.org>
see https://github.com/ziuziakowska/opensbi/tree/mocha-devel for the OpenSBI driver code that uses these bindings. Signed-off-by: Alice Ziuziakowska <a.ziuziakowska@lowrisc.org>
Signed-off-by: Alice Ziuziakowska <a.ziuziakowska@lowrisc.org>
Signed-off-by: Alice Ziuziakowska <a.ziuziakowska@lowrisc.org>
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I've tested this pull request based on the following instructions.
Run the Verilator simulator:
build/lowrisc_mocha_top_chip_verilator_0/sim-verilator/Vtop_chip_verilator -E build/sw/device/bootrom/bootrom -E build/sw/opensbi_with_opensbi_test_payload/fw_payload.elfToggle the GPIO bootstrap pin:
echo 'h08' > gpio0_writeCheck UART output in uart0.log should be:
Boot ROM: v00.01.00
No valid slot found, default to DRAM
Jumping to: 0x80000000
In trace_hart_0.dasm it should jump to 0x8000000 eventually and it should look something like this:
103511 0x1000385c M (0x00000597) DASM(00000597)
103512 0x10003860 M (0x32458593) DASM(32458593)
103515 0x10003864 M (0x00009602) DASM(00009602)
103544 0x80000000 M (0x74746073) DASM(74746073) <- in OpenSBI now
103564 0x80000004 M (0x12001033) DASM(12001033)
103584 0x80000008 M (0x00000697) DASM(00000697)
103604 0x8000000c M (0x0c0696b3) DASM(0c0696b3)
103624 0x80000010 M (0x00004285) DASM(00004285)
103644 0x80000012 M (0x0c56f6b3) DASM(0c56f6b3)
103664 0x80000016 M (0x00040297) DASM(00040297)
103684 0x8000001a M (0x04a2a29b) DASM(04a2a29b)
103705 0x8000001e M (0x00d2c023) DASM(00d2c023)
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This PR adds a build step for OpenSBI - an M-mode firmware and "bootloader" - as well as associated changes to the boot ROM for it. The https://github.com/lowRISC/opensbi/tree/mocha-devel fork is used which adds drivers for enough Opentitan devices to get it printing and booting. The firmware is built with a test payload in the Mocha tree that performs an SBI call to print the test success message for FPGA platforms, and to report success to the DV status register.
This PR also adds a basic devicetree hardware description of Mocha, which is baked-in to the ROM. The bindings used should be kept in sync with our OpenSBI fork.
The boot ROM is modified to pass this pointer in the
a1register, and the hart id (0) in thea0register, as expected by OpenSBI.The boot ROM is also modified to jump to the DRAM base by default if no boot magic number is found, as modifying the linkerscript of OpenSBI to include the magic number and boot address caused a lot of issues, and it means next stage software does not need intrusive modification to run.