V2 — programmable protocol emulator

V2 delivers a reprogrammable protocol emulator ASIC with two independent timing engines, SPI host control, and triggered capture. This is the V2 milestone, with further verification planned before the final competition submission. Python package and runtime versions remain 2.0.0rc1.

Design and tools

• Two 25 MHz engines, each with 64 words of 24-bit program memory and 16-entry TX/RX queues.
• UART TX/RX examples at 115200 baud and 1 Mbaud; SPI modes 0–3 in controller and target roles; I²C at 100/400 kHz in controller and target roles.
• Pin ownership, open-drain configuration, input filtering and 32 triggered capture records.
• V2 defaults for ASIC metadata and build/test entrypoints, with explicit V1 regression targets.
• Sphinx architecture, ISA, assembler/toolchain, example-program and verification documentation.

Physical settings remain 6×4 tiles, 40 ns clock, 1.5 ns maximum transition and 0.25 ns uncertainty. The 8×4 template remains deferred.

Validation

The validated source passed 699 pytest cases, all V1/V2 RTL suites, both tops' Verilator lint and Yosys synthesis, five induction proofs, and six mutation checks. Strict Sphinx HTML and all 14 executable examples passed. The selected netlist passed the current 14-scenario gate-level suite and four-state startup/reset/state-loss audit.

The selected local TT checkpoint recovery passed all required physical checks, nine stock prechecks, mapping and full-geometry checks. Minimum extracted setup slack is 18.456291 ns and minimum hold slack is 0.054473 ns across the three corners. Gate-level simulation uses functional cell models; extracted timing is checked separately.

Release provenance

Component	Revision
v2 tag / merged PR #15	ebd05cd434bdb1d9d238d824f7ea4321934b2c25
Validated release-selection documentation	e4565e7349f2dd102d64998b3d9376d32668b8ba
Software packages and current netlist tests	881495cb4d5a6270f5dd7625b1787d83f3059827
Selected physical layout	447b3dfd0986d473c71afa28efafb3a5cff48da7

The merged tag's file tree exactly matches the validated release-selection revision. The physical and software source revisions produce identical Yosys-elaborated designs after removing only source-location annotations, and their prepared V2 configurations match.

The owner selected the completed local TT recovery after the hosted job reached its six-hour limit. It used the pinned stock CMOS5L flow scripts, a verified checkpoint and recorded execution/debug settings, with no custom routing-script substitution or checkpoint ECO. The original timeout and failed parent route remain in the evidence. This release records a local checkpoint recovery, not a completed uninterrupted hosted route or a mixed-source common-source acceptance-checker pass.

• Full physical evidence and checksum
• Download the 2.74 GB evidence archive
• Archive SHA-256: 2d742a7604d573617cf5f0471e435858afdd9729505c9c9ebb275c075942b466
• Release evidence documentation

Downloads and operating limits

Assets include tagged source, original software/physical source archives, Python wheel and sdist, committed HTML documentation, executable examples, the selected GDS/netlist, verification records, release-manifest.json and SHA256SUMS. Historical evidence records retain their original source identities and candidate-status fields; the release manifest records this milestone's components.

The CLI remains V1; V2 assembly, disassembly, model execution and loading use the Python APIs. Program and capture storage are volatile: after state loss, reset, reconfigure, reload programs/queues and restart. The 1 Mbaud UART duplex examples are bounded/preloaded bursts; the 1 MHz SPI host cannot sustain arbitrary continuous traffic at that rate. No silicon/FPGA demonstration or competition acceptance is claimed.

Track 2 covers expanded RTL properties, compositional-assumption review, broader mutations and a Lean ISA model.

V2 local acceptance evidence — af573c5

Full evidence for V2 local acceptance of source af573c5fef6f96b4c2fbd400e6565b3b41f54aef, completed October 8, 2026.

The successful-run archive preserves the original source snapshot, manifests, reports, logs, netlist, layout and full-geometry rendering, plus successful final-stage outputs. It contains 1,085 files (about 392 MiB compressed); every file was hash-checked against its retained original. Failed-run directories are excluded. Original machine paths and container names remain in hash-bound provenance; checking the accepted bundle does not require those locations.

Download the archive and SHA256SUMS, verify using shasum -a 256 -c SHA256SUMS, extract it, and run python3 accepted/source/tools/check_v2.py accepted. This verifies retained acceptance evidence; it does not rerun the physical flow.

Results: 560 Python tests, existing RTL suites, five formal proofs, six mutations, 14 gate-level suites and nine precheck checks. Required physical/electrical violations are zero, worst setup slack is +18.370074 ns and worst hold slack is +0.052527 ns. The fixed 40 ns / 1.5 ns / 0.25 ns constraints and full storage capacities remain unchanged.

The release tag points to the restructured development source containing the evidence index. It does not relabel the archive's original source or transfer physical acceptance to the rewritten history. development-validation.json records fresh functional validation of the four development branch tips separately.

This is an evidence prerelease, not a shuttle submission or declaration that verification is finished. V1 remains the latest product release. The v2-current Draft PR remains open for stronger tests and formal verification.

V1.0.0 — programmable protocol emulator

V1 provides a single programmable timing engine with 64 x 24-bit instruction memory, a four-byte TX FIFO, SPI programming/control, Python tooling, and firmware-driven UART 8N1 transmission at 1 Mbaud and approximately 115200 baud. The implementation targets Tiny Tapeout IHP CMOS5L, 6x4 tiles, and a 25 MHz system clock.

Source: 00b048acaafb5baf27da79127686921e345929fa
Final acceptance run 35951164651 · Electrical closure PR #9

Validation

The final merged revision passed functional, GDS, precheck, gate-level, and acceptance jobs. Downloaded artifacts independently passed the repository acceptance checker, with source hashes, submitted netlist, and pinned primitive models verified against the manifests.

• 205 Python tests, three core differential suites, three pin-level RTL suites, RTL lint, and formal induction passed.
• All three routed-netlist gate-level suites passed, including UART at both rates.
• All nine Tiny Tapeout prechecks passed, including KLayout CMOS5L DRC. Magic DRC and LVS passed.
• Zero slew, fanout, capacitance, routing DRC, antenna, and unannotated-signal violations at every required corner. The transition constraint remains 1.5 ns.
• Worst routed setup/hold slack: +21.053364 / +0.106182 ns.
• Standard-cell area: 244113 um2; utilization: 27.0510%.

The flow uses LibreLane 3.1.0.dev3 and IHP-Open-PDK revision 2bbec755dc67ca3db0261c3d6163e15735d66710. Configuration and provenance records are included in the evidence bundle.

Assets

• protocol-emulator-v1.0.0-source.tar.gz: source snapshot at the accepted revision.
• protocol-emulator-v1.0.0-submission.tar.gz: GDS, OAS, LEF, routed netlist, SPEF, resolved configuration, statistics, and source/PDK identities.
• protocol-emulator-v1.0.0-evidence.tar.gz: all final-run artifacts, detailed physical reports, test results, firmware and waveform evidence, manifests, independent verification, and per-file checksums.
• protocol-emulator-v1.0.0-physical-summary.json: machine-readable acceptance summary.
• SHA256SUMS: checksums for the four release assets above.

Limits

This is a verified design release; no FPGA or silicon operation has been demonstrated. Gate-level tests are functional routed-netlist simulation; extracted STA establishes timing separately. Positive timing slack is not an Fmax measurement.

The host SPI contract is limited to 1 MHz. Four queued bytes can transmit consecutively at 1 Mbaud, but the current request/response refill protocol does not support indefinite 1-Mbaud streaming. UART receive, additional engines, on-chip capture/replay, and emulated SPI/I2C firmware remain post-V1 work.