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V2 delivers a reprogrammable protocol emulator ASIC with two independent timing engines, SPI host control, and triggered capture. This is the V2 milestone, with further verification planned before the final competition submission. Python package and runtime versions remain 2.0.0rc1.
Design and tools
- Two 25 MHz engines, each with 64 words of 24-bit program memory and 16-entry TX/RX queues.
- UART TX/RX examples at 115200 baud and 1 Mbaud; SPI modes 0–3 in controller and target roles; I²C at 100/400 kHz in controller and target roles.
- Pin ownership, open-drain configuration, input filtering and 32 triggered capture records.
- V2 defaults for ASIC metadata and build/test entrypoints, with explicit V1 regression targets.
- Sphinx architecture, ISA, assembler/toolchain, example-program and verification documentation.
Physical settings remain 6×4 tiles, 40 ns clock, 1.5 ns maximum transition and 0.25 ns uncertainty. The 8×4 template remains deferred.
Validation
The validated source passed 699 pytest cases, all V1/V2 RTL suites, both tops' Verilator lint and Yosys synthesis, five induction proofs, and six mutation checks. Strict Sphinx HTML and all 14 executable examples passed. The selected netlist passed the current 14-scenario gate-level suite and four-state startup/reset/state-loss audit.
The selected local TT checkpoint recovery passed all required physical checks, nine stock prechecks, mapping and full-geometry checks. Minimum extracted setup slack is 18.456291 ns and minimum hold slack is 0.054473 ns across the three corners. Gate-level simulation uses functional cell models; extracted timing is checked separately.
Release provenance
| Component | Revision |
|---|---|
v2 tag / merged PR #15 |
ebd05cd434bdb1d9d238d824f7ea4321934b2c25 |
| Validated release-selection documentation | e4565e7349f2dd102d64998b3d9376d32668b8ba |
| Software packages and current netlist tests | 881495cb4d5a6270f5dd7625b1787d83f3059827 |
| Selected physical layout | 447b3dfd0986d473c71afa28efafb3a5cff48da7 |
The merged tag's file tree exactly matches the validated release-selection revision. The physical and software source revisions produce identical Yosys-elaborated designs after removing only source-location annotations, and their prepared V2 configurations match.
The owner selected the completed local TT recovery after the hosted job reached its six-hour limit. It used the pinned stock CMOS5L flow scripts, a verified checkpoint and recorded execution/debug settings, with no custom routing-script substitution or checkpoint ECO. The original timeout and failed parent route remain in the evidence. This release records a local checkpoint recovery, not a completed uninterrupted hosted route or a mixed-source common-source acceptance-checker pass.
- Full physical evidence and checksum
- Download the 2.74 GB evidence archive
- Archive SHA-256:
2d742a7604d573617cf5f0471e435858afdd9729505c9c9ebb275c075942b466 - Release evidence documentation
Downloads and operating limits
Assets include tagged source, original software/physical source archives, Python wheel and sdist, committed HTML documentation, executable examples, the selected GDS/netlist, verification records, release-manifest.json and SHA256SUMS. Historical evidence records retain their original source identities and candidate-status fields; the release manifest records this milestone's components.
The CLI remains V1; V2 assembly, disassembly, model execution and loading use the Python APIs. Program and capture storage are volatile: after state loss, reset, reconfigure, reload programs/queues and restart. The 1 Mbaud UART duplex examples are bounded/preloaded bursts; the 1 MHz SPI host cannot sustain arbitrary continuous traffic at that rate. No silicon/FPGA demonstration or competition acceptance is claimed.
Track 2 covers expanded RTL properties, compositional-assumption review, broader mutations and a Lean ISA model.