v0.2 — Governance, CI, and citation-backed roadmap
Overview
First tagged release of phoenix-sdr-dsp. All 12 shipped milestones (M1–M12 per the master prompt canonical §16 sequence) remain silicon-validated on physical AMD Phoenix XDNA1 NPU and pass the full regression suite bit-accurately in 62.42 s.
Hardware & toolchain
- Target APU: AMD Ryzen 9 7940HS (Phoenix)
- NPU: AMD XDNA1 — 4×5 AIE2 tile array (VLIW SIMD, 512-bit vector datapath)
- Host: Windows 11 Pro 25H2
- Toolchain: MLIR-AIE / IRON + Peano LLVM-AIE + Xilinx Runtime (XRT)
What's new since initial release
Governance & reproducibility
CITATION.cff(BOM-free, cff-version 1.2.0)CODE_OF_CONDUCT.md(Contributor Covenant 2.1)SECURITY.md,CONTRIBUTING.md,pull_request_template.md- Issue templates (silicon bug, bug report, feature request)
toolchain.yaml— canonical machine-readable toolchain pin.editorconfig,.gitattributes
Continuous integration
- 4-job CI: Lint (ruff), Validate CFF + YAML (cffconvert), CPU reference tests (M12 NTT/INTT), Markdown link check
- All green on the release commit
- Dependabot enabled for weekly GitHub Actions updates
- CI badge in README
Documentation
docs/ROADMAP.md— two-track roadmap:- Track 1 (NPU DSP kernels): active, no hardware blockers
- Track 2 (SDR integration): deferred pending hardware acquisition
- Every technical claim backed by primary sources (AMD official docs, Linux amdxdna kernel driver docs, IEEE Micro 2024, Cooley-Tukey 1965, PLOS ONE Kyber NTT, arXiv 2601.17806 on ML-KEM)
- Honest divergence disclosure: repo's M-numbering vs master prompt §16
- LICENSE.md duplicate removed (canonical LICENSE retained, MIT still detected)
Silicon-validated milestones (12/12 PASS)
| M# | Kernel | Bit-exact? |
|---|---|---|
| M3 | SAXPY vector | Yes |
| M5 | 8-tap FIR filter | Yes |
| M6 | Complex mixer / NCO | Yes |
| M7 | Power / RSSI detector | Yes |
| M8 | Fused DSP pipeline | Yes |
| M9 | 4-column parallel FIR | Yes |
| M10 | Modular arithmetic (Barrett, q=3329) |
Yes |
| M11 | Radix-2 NTT butterfly | Yes |
| M12 | CPU NTT/INTT reference | Yes |
| M13 | 16-point NPU NTT | Yes |
| M14 | 256-point vectorized NPU NTT | Yes |
| M15 | NPU INTT + cyclic poly mult | Yes |
Next (v0.3 series)
- Directory renumbering to align with §16 canonical sequence
- M16 CPU FFT reference (radix-2 Cooley-Tukey)
- M17 O(N log N) NPU FFT via radix-2 butterflies (current shipped FFT is direct O(N²) DFT)
- M19 complex FIR (upgrade real-valued FIR)
- M20 polyphase decimation/interpolation
See docs/ROADMAP.md for the full canonical §16 milestone plan.
Acknowledgments
Built on the open-source AMD/Xilinx AI Engine toolchain (mlir-aie, llvm-aie/Peano, announced June 2024).