Phoenix SDR-DSP v1.0.1-rc.4: research provenance snapshot

Scope

This prerelease adds a forward-looking Apache-2.0 default, retained file-level exceptions, audited third-party provenance, and Zenodo-ready citation metadata.

Documentation

• The clean-clone Windows flow documents direct activation through third_party\mlir-aie\ironenv\Scripts\Activate.ps1 and D:-drive-safe environment setup.
• The M21 DDC display equation uses GitHub-compatible matched delimiters, fixing the prior Missing or unrecognized delimiter for \big preview error.
• No new NPU execution or AIE compilation was performed for this metadata release; existing milestone evidence boundaries are unchanged.

Integrity and provenance

• Third-party origins, immutable revisions, local hashes, NIST ACVP notice obligations, and extraction rules are recorded in the repository.
• CI passed for commit 67f06736e3f3e57ae952e4c79d2c393264d6b19a: https://github.com/midhatn/phoenix-sdr-dsp/actions/runs/32167285428

Phoenix SDR-DSP v1.0.1-rc.3

Clean-clone release candidate with a one-command Windows flow.

From the cloned repository, run:

py .\install

The stdlib-only launcher provisions the pinned XRT, MLIR-AIE/IRON, Peano, pyxrt, and PQC reference environment. Only after installation succeeds does it invoke the unchanged canonical 34-entry regression runner. The canonical runner SHA-256 remains 742591321ac5dc3069a51ded4e198905367f8dc6261df8c3ebae20b5e333fbad.

This release also replaces unsupported \operatorname notation in maintained M32 mathematics and adds regression coverage for GitHub math compatibility.

CI: https://github.com/midhatn/phoenix-sdr-dsp/actions/runs/32152354416

Phoenix SDR-DSP v1.0.1-rc.2: corrected clean-drive gate

Supersedes RC.1 for clean-drive evaluation. The first independent Windows run of RC.1 passed repository, compilation, header, and canonical-runner hash gates, then stopped before hardware because NumPy was absent. RC.2 adds an explicit -InstallHostDependencies switch pinned to numpy==2.5.2 and records that failure in the publication-readiness history. The canonical runner remains SHA-256 742591321ac5dc3069a51ded4e198905367f8dc6261df8c3ebae20b5e333fbad. CI passed at commit 3b81abb. No new NPU run is claimed.

Phoenix SDR-DSP v1.0.1-rc.1: research reproduction gate

Research release candidate for the audited documentation, CI, citation, arithmetic-safety, and clean-drive reproduction changes at commit d67bb64.

The canonical run_all_silicon_tests.py remains byte-identical with SHA-256 742591321ac5dc3069a51ded4e198905367f8dc6261df8c3ebae20b5e333fbad. This prerelease does not claim a new 34-entry silicon rerun. Final release remains gated on the documented Windows/Phoenix clean-drive procedure.

Deterministic local git-archive SHA-256 values:

8055ab6701e4e2704c78296e3043d81c958edf8497ca46492ad9410c5e07b6a4  phoenix-sdr-dsp-v1.0.1-rc.1.tar.gz
85bb08c4ce7eddd86f01afaa453878d99d120e4310df45d90386f5ed4d58af81  phoenix-sdr-dsp-v1.0.1-rc.1.zip

GitHub also provides tag-generated Source code archives on this release page. The deterministic local archives are retained for later journal archive deposit; binary asset upload was unavailable in the publication environment.

Independent clean-drive result

Superseded by v1.0.1-rc.2. On Windows PowerShell 7.6.5 with Python 3.13.15, RC.1 passed repository identity, Python compilation, public-header inventory, and canonical-runner SHA-256 checks, then stopped before hardware because NumPy was absent. This is retained as a prerequisite failure, not a host-suite or silicon pass.

v1.0.0 — Post-Quantum Cryptography closure (M32 ML-KEM + M33 ML-DSA)

Phoenix SDR / DSP reaches its first stable milestone. The kernel library that opened at 16 / 16 (v0.4.0) now closes at 34 / 34 PASS on Phoenix NPU1 with the full Post-Quantum Cryptography track landed and silicon-validated bit-exact against the NIST ACVP-Server known-answer tests.

What's in v1.0.0

FIPS 203 ML-KEM — M32b (NTT over Z_3329), M32c (FIPS 202 Keccak-f[1600] / SHA-3 / SHAKE), M32d (K-PKE component), M32e (ML-KEM-{512, 768, 1024} KeyGen / Encaps / Decaps composer). Reference oracle: kyber-py 1.0.1.

FIPS 204 ML-DSA — M33a (NTT over Z_8380417), M33b (rounding + hint), M33c (SHAKE reuse per FIPS 204 §3.3.5), M33d (ML-DSA-{44, 65, 87} KeyGen composer, 75 / 75), M33e (Sign_internal + Verify_internal composer, 180 / 180 including 72 must-reject tampered signatures across both externalMu paths). Reference oracle: dilithium-py 1.4.0.

Full closure notes: docs/PQC_COMPLETE_V1.md.

Reproduction (Windows / Ryzen Phoenix laptop)

conda deactivate
git clone https://github.com/midhatn/phoenix-sdr-dsp.git
cd phoenix-sdr-dsp
py .\install.py
py .\run_all_silicon_tests.py

Since v1.0.0, install.py auto-installs the pinned PQC reference packages (kyber-py==1.0.1, dilithium-py==1.4.0, pytest) into the ironenv it just created. SHAKE / SHA-3 primitives come from the CPython hashlib standard library, so no separate SHAKE / Keccak wheel is required. A fresh-clone dry run on a blank disk finished 34 / 34 PASS in 38.02 s.

Prerequisites: AMD Ryzen Phoenix / Hawk Point NPU, AMD NPU driver, and the toolchain pins in docs/M2_TOOLCHAIN_PIN.md (Xilinx XRT, Xilinx MLIR-AIE v1.4.1 + pin 3ca0193, LLVM Peano 21.0.0.2026080301+c9c5ecb7).

Silicon coverage at v1.0.0

33 milestones, 34 test invocations, all PASS on Phoenix NPU1:
M3, M5–M15, M15b, M17, M17p, M19–M27, and the PQC track M32b / M32c / M32d / M32e + M33a / M33b / M33d / M33e.

The Kernel.org Phoenix topology is 4 × 5 (four columns × five rows of AIE-ML tiles). All 34 tests dispatch on this topology through the pinned MLIR-AIE + Peano toolchain.

Vector provenance

NIST ACVP-Server response vectors for ML-KEM (keyGen / encapDecap) and ML-DSA (keyGen / sigGen / sigVer) are vendored under tests/m32_mlkem/vectors/ and tests/m33_mldsa/vectors/. Source: usnistgov/ACVP-Server.

Standards and specifications

• FIPS 203, 2024-08-13 — Module-Lattice-Based Key-Encapsulation Mechanism Standard (ML-KEM)
• FIPS 204, 2024-08-13 — Module-Lattice-Based Digital Signature Standard (ML-DSA)
• FIPS 202 — SHA-3 Standard: Permutation-Based Hash and Extendable-Output Functions

Prior tags (unchanged)

v0.6.0 (988ba6c), v0.5.0 (e63bdbe), v0.4.0 (7127315), v0.3.0 (8a7a152), v0.2 (647859d).

v0.6.0 -- M26 fused QAM-16 receiver with soft-decision LLR demapping

v0.6.0 -- M26 fused QAM-16 receiver with soft-decision LLR demapping

24th silicon regression entry, first LLR-emitting kernel in the suite.

Extends the M25 receiver core (on-tile NCO derotator with Taylor sin/cos

• pi/2 fold, linear fractional interpolator, Gardner 1986 TED, Rondeau-
  tuned PI loop filters) with a Gray-labelled QAM-16 hard-decision slicer,
  a decision-directed order-M phase detector, and a max-log axis-separable
  soft-output demapper. Single @iron.jit entry point qam16_rx with the
  first three-argument kernel signature (in_iq, out_iq, out_llr).

Silicon PASS on Phoenix NPU1, seed 826 (2026-08-15):
gate (a) acquisition max_err = 0.0039 (atol 0.10)
gate (b1) magnitude-class median = 0.0020 (atol 0.15)
gate (b2) RMS(z - qam16_slice(z)) = 0.0027 (atol 0.10)
gate (c) diagnostic-only per Amendment #1 (timing drift between
independent DD + Gardner integrators; see docs/M26_DESIGN.md
sec 4)
gate (d) LLR MSB b3 = b1 = 1.000 (threshold 0.85)
gate (d) LLR LSB b2 = b0 = 1.000 (threshold 0.75)

Sandbox transliteration bit-exact on hardSym and LLR buffers, seeds
826 and 827 (tools/m26_kernel_transliteration_check.py).

Published contract: 23/23 -> 24/24 silicon-validated milestones.

Full narrative, both bring-up incidents, and references are in the
squash-of-history commit and docs/M26_DESIGN.md.

Phoenix SDR-DSP v0.4.0 — Radix-4 Stockham FFT on Phoenix NPU

Highlights

M17 is now an O(N log N) radix-4 Stockham FFT on Phoenix NPU, not the O(N^2) direct DFT shipped in v0.3.0.

Silicon result (N=64, NPU1 / AIE2)

Metric	Value
Peak bins	[4, 12, 20] (match numpy)
Max abs error	8e-6
RMS abs error	1e-6
SNR	138.79 dB
NaNs	0

What broke, what fixed it

IRON Worker defaulted to AIETargetModel::getDefaultCoreStackSize() = 0x400 (1 KB). The general-stage frame overflowed into ObjectFifo buffers at tile offset 0x400 and produced an 8-float tiling / 32-NaN pattern. Stage 0 fit in 1 KB and was already bit-correct.

Fix: Worker(..., stack_size=0x4000) (same value as AMD FFT_R4_AIE single_core.py) plus alignas(aie::vector_decl_align) on butterfly_in / butterfly_out / twiddle_buf.

Not in this tag

• IFFT / round-trip test
• Merge of feat/m17-radix2-fft-npu into main
• Retirement of the M17 direct-DFT kernel from run_all_silicon_tests.py

Phoenix SDR-DSP v0.3.0 — Silicon Regression Expanded to 16 Milestones

Highlights

Silicon regression: 12 → 16 milestones. run_all_silicon_tests.py now dispatches four additional silicon-validated tests that had been living outside the runner since the v0.2.1 renumbering.

Newly integrated milestones

ID	Kernel	Silicon workload
M9b	4-column parallel multi-stage demodulator pipeline	4096 I/Q samples × 4 cores
M15b	Negacyclic polynomial multiplication in Z_q[x]/(x^N+1) — the Kyber ring	N=256, q=3329
M17	64-point direct O(N²) DFT NPU kernel in bfloat16	64 bins per frame
M17p	4-column parallel variant of M17	64 frames × 4 cores

Each was already silicon-validated independently; this release wires them into the same regression harness that runs M3 and M5–M15.

Runner quality fix

On any FAILED test the runner now returns exit code 1. Previously it printed a failure banner but still exited 0, which meant CI would report green on silicon failures. Meaningful exit semantics are now restored for future automation.

Audit trail

tests/RENUMBERING.md updated to check off two completed follow-ups:

• ✅ v0.2.1 — M16 CPU FFT reference implementation (radix-2 Cooley-Tukey with iterative bit-reversed variant, cross-validated across 8 sizes with Parseval energy conservation exact to double precision).
• ✅ v0.3.0 — Runner integration of the four renamed FFT/pipeline tests.

Remaining open item: ship an M17 radix-butterfly O(N log N) implementation to replace the current direct O(N²) DFT, using the M16 iterative bit-reversed CPU reference as the dataflow template and the M11 finite-field radix-2 NTT butterfly as the silicon arithmetic template.

Verification

All 16 tests confirmed bit-accurate on AMD Ryzen 9 7940HS Phoenix NPU1 (XDNA1 / AIE2 / Win11) prior to release. CI green on the release commit (8a7a152).

Cumulative status through v0.3.0

• 12/12 (M3, M5–M15) silicon-accurate — established through v0.2.0.
• +4 (M9b, M15b, M17, M17p) silicon-accurate — added to runner in v0.3.0.
• CPU references — M12 NTT + M16 FFT, both in CI on every commit.
• Test count in cloud CI: unchanged (silicon tests still local-only; CPU tests run on GitHub-hosted runners).

References

• Cooley, J. W. and Tukey, J. W. (1965). "An algorithm for the machine calculation of complex Fourier series." Mathematics of Computation 19(90): 297–301.
• Isabelle/AFP CRYSTALS-Kyber formalization outline (Kyber ring Z_q[x]/(x^N+1), N=256, q=3329): https://isa-afp.org/browser_info/current/AFP/CRYSTALS-Kyber/outline.pdf.
• AMD XDNA architecture: https://www.amd.com/en/technologies/xdna.html.
• Xilinx/mlir-aie IRON docs v1.4.1: https://xilinx.github.io/mlir-aie/1.4.1/.
• Xilinx/llvm-aie (Peano AIE2 backend): https://github.com/Xilinx/llvm-aie.

Full changelog: v0.2...v0.3.0

v0.2 — Governance, CI, and citation-backed roadmap

Overview

First tagged release of phoenix-sdr-dsp. All 12 shipped milestones (M1–M12 per the master prompt canonical §16 sequence) remain silicon-validated on physical AMD Phoenix XDNA1 NPU and pass the full regression suite bit-accurately in 62.42 s.

Hardware & toolchain

• Target APU: AMD Ryzen 9 7940HS (Phoenix)
• NPU: AMD XDNA1 — 4×5 AIE2 tile array (VLIW SIMD, 512-bit vector datapath)
• Host: Windows 11 Pro 25H2
• Toolchain: MLIR-AIE / IRON + Peano LLVM-AIE + Xilinx Runtime (XRT)

What's new since initial release

Governance & reproducibility

• CITATION.cff (BOM-free, cff-version 1.2.0)
• CODE_OF_CONDUCT.md (Contributor Covenant 2.1)
• SECURITY.md, CONTRIBUTING.md, pull_request_template.md
• Issue templates (silicon bug, bug report, feature request)
• toolchain.yaml — canonical machine-readable toolchain pin
• .editorconfig, .gitattributes

Continuous integration

• 4-job CI: Lint (ruff), Validate CFF + YAML (cffconvert), CPU reference tests (M12 NTT/INTT), Markdown link check
• All green on the release commit
• Dependabot enabled for weekly GitHub Actions updates
• CI badge in README

Documentation

• docs/ROADMAP.md — two-track roadmap:
  • Track 1 (NPU DSP kernels): active, no hardware blockers
  • Track 2 (SDR integration): deferred pending hardware acquisition
  • Every technical claim backed by primary sources (AMD official docs, Linux amdxdna kernel driver docs, IEEE Micro 2024, Cooley-Tukey 1965, PLOS ONE Kyber NTT, arXiv 2601.17806 on ML-KEM)
• Honest divergence disclosure: repo's M-numbering vs master prompt §16
• LICENSE.md duplicate removed (canonical LICENSE retained, MIT still detected)

Silicon-validated milestones (12/12 PASS)

M#	Kernel	Bit-exact?
M3	SAXPY vector	Yes
M5	8-tap FIR filter	Yes
M6	Complex mixer / NCO	Yes
M7	Power / RSSI detector	Yes
M8	Fused DSP pipeline	Yes
M9	4-column parallel FIR	Yes
M10	Modular arithmetic (Barrett, q=3329)	Yes
M11	Radix-2 NTT butterfly	Yes
M12	CPU NTT/INTT reference	Yes
M13	16-point NPU NTT	Yes
M14	256-point vectorized NPU NTT	Yes
M15	NPU INTT + cyclic poly mult	Yes

Next (v0.3 series)

• Directory renumbering to align with §16 canonical sequence
• M16 CPU FFT reference (radix-2 Cooley-Tukey)
• M17 O(N log N) NPU FFT via radix-2 butterflies (current shipped FFT is direct O(N²) DFT)
• M19 complex FIR (upgrade real-valued FIR)
• M20 polyphase decimation/interpolation

See docs/ROADMAP.md for the full canonical §16 milestone plan.

Acknowledgments

Built on the open-source AMD/Xilinx AI Engine toolchain (mlir-aie, llvm-aie/Peano, announced June 2024).