Phoenix SDR-DSP v0.3.0 — Silicon Regression Expanded to 16 Milestones
Highlights
Silicon regression: 12 → 16 milestones. run_all_silicon_tests.py now dispatches four additional silicon-validated tests that had been living outside the runner since the v0.2.1 renumbering.
Newly integrated milestones
| ID | Kernel | Silicon workload |
|---|---|---|
| M9b | 4-column parallel multi-stage demodulator pipeline | 4096 I/Q samples × 4 cores |
| M15b | Negacyclic polynomial multiplication in Z_q[x]/(x^N+1) — the Kyber ring |
N=256, q=3329 |
| M17 | 64-point direct O(N²) DFT NPU kernel in bfloat16 |
64 bins per frame |
| M17p | 4-column parallel variant of M17 | 64 frames × 4 cores |
Each was already silicon-validated independently; this release wires them into the same regression harness that runs M3 and M5–M15.
Runner quality fix
On any FAILED test the runner now returns exit code 1. Previously it printed a failure banner but still exited 0, which meant CI would report green on silicon failures. Meaningful exit semantics are now restored for future automation.
Audit trail
tests/RENUMBERING.md updated to check off two completed follow-ups:
- ✅ v0.2.1 — M16 CPU FFT reference implementation (radix-2 Cooley-Tukey with iterative bit-reversed variant, cross-validated across 8 sizes with Parseval energy conservation exact to double precision).
- ✅ v0.3.0 — Runner integration of the four renamed FFT/pipeline tests.
Remaining open item: ship an M17 radix-butterfly O(N log N) implementation to replace the current direct O(N²) DFT, using the M16 iterative bit-reversed CPU reference as the dataflow template and the M11 finite-field radix-2 NTT butterfly as the silicon arithmetic template.
Verification
All 16 tests confirmed bit-accurate on AMD Ryzen 9 7940HS Phoenix NPU1 (XDNA1 / AIE2 / Win11) prior to release. CI green on the release commit (8a7a152).
Cumulative status through v0.3.0
- 12/12 (M3, M5–M15) silicon-accurate — established through v0.2.0.
- +4 (M9b, M15b, M17, M17p) silicon-accurate — added to runner in v0.3.0.
- CPU references — M12 NTT + M16 FFT, both in CI on every commit.
- Test count in cloud CI: unchanged (silicon tests still local-only; CPU tests run on GitHub-hosted runners).
References
- Cooley, J. W. and Tukey, J. W. (1965). "An algorithm for the machine calculation of complex Fourier series." Mathematics of Computation 19(90): 297–301.
- Isabelle/AFP CRYSTALS-Kyber formalization outline (Kyber ring
Z_q[x]/(x^N+1), N=256, q=3329): https://isa-afp.org/browser_info/current/AFP/CRYSTALS-Kyber/outline.pdf. - AMD XDNA architecture: https://www.amd.com/en/technologies/xdna.html.
- Xilinx/mlir-aie IRON docs v1.4.1: https://xilinx.github.io/mlir-aie/1.4.1/.
- Xilinx/llvm-aie (Peano AIE2 backend): https://github.com/Xilinx/llvm-aie.
Full changelog: v0.2...v0.3.0