v0.6.0 -- M26 fused QAM-16 receiver with soft-decision LLR demapping
v0.6.0 -- M26 fused QAM-16 receiver with soft-decision LLR demapping
24th silicon regression entry, first LLR-emitting kernel in the suite.
Extends the M25 receiver core (on-tile NCO derotator with Taylor sin/cos
- pi/2 fold, linear fractional interpolator, Gardner 1986 TED, Rondeau-
tuned PI loop filters) with a Gray-labelled QAM-16 hard-decision slicer,
a decision-directed order-M phase detector, and a max-log axis-separable
soft-output demapper. Single @iron.jit entry point qam16_rx with the
first three-argument kernel signature (in_iq, out_iq, out_llr).
Silicon PASS on Phoenix NPU1, seed 826 (2026-08-15):
gate (a) acquisition max_err = 0.0039 (atol 0.10)
gate (b1) magnitude-class median = 0.0020 (atol 0.15)
gate (b2) RMS(z - qam16_slice(z)) = 0.0027 (atol 0.10)
gate (c) diagnostic-only per Amendment #1 (timing drift between
independent DD + Gardner integrators; see docs/M26_DESIGN.md
sec 4)
gate (d) LLR MSB b3 = b1 = 1.000 (threshold 0.85)
gate (d) LLR LSB b2 = b0 = 1.000 (threshold 0.75)
Sandbox transliteration bit-exact on hardSym and LLR buffers, seeds
826 and 827 (tools/m26_kernel_transliteration_check.py).
Published contract: 23/23 -> 24/24 silicon-validated milestones.
Full narrative, both bring-up incidents, and references are in the
squash-of-history commit and docs/M26_DESIGN.md.