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v1.0.0-preview

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@ortanaV2 ortanaV2 released this 20 Jul 14:57
v1.0.0-preview
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Full Changelog: https://github.com/ortanaV2/Isonic/commits/v1.0.0-preview

Isonic's first release - a schematic-capture and live logic simulator for building digital circuits from single gates up to full CPUs, with an eye toward doubling as the schematic-entry foundation for PCB design.

image

Implemented

  • Live logic simulation with real-time signal propagation across nets
  • Multi-layer PCB-style routing — named, colored layers with GND/POWER roles, connected via vias
  • Circuit diagnostics overlay — flags bus conflicts, overwritten drivers, floating pins, and fan-out overloads directly on the canvas
  • Full undo/redo for structural edits, including mouse back/forward button support
  • File menu — New Schematic, New Window, Open, Save, Save As, Close Window, with unsaved-changes prompts
  • Custom .isonic save format — layers, components, wiring, vias, and EEPROM contents all round-trip
  • Settings popup — configurable autosave interval, Layers panel corner, and fully rebindable tool/action keybinds, persisted per user
  • EEPROM (AT28C64B) data editor — view and edit memory contents directly without wiring up address/data pins
  • Custom IC framework — define a chip's pinout and behavior once, place it like any built-in part
  • Built-in IC catalog: logic gates (AND/OR/NOT/NAND/NOR/XOR), 8:1 and dual 4:1 multiplexers, 1:8 and dual 1:4 demultiplexers, tri-state buffer, D-latch, 12-bit binary counter, 555 timer, AT28C64B EEPROM

Notes

  • Windows only for now — see the README for controls and installation
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