v1.3.2-patch

Full Changelog: v1.3.1...v1.3.2

Patched

• Fixed blurry UI text on Windows 11 displays with scaling above 100% — the app now declares proper DPI awareness and renders UI text at real device pixels instead of being bitmap-stretched by Windows.
• Fixed Undo/Redo (and other letter-shortcut) keybinds firing the wrong action on QWERTZ (German/Swiss) keyboard layouts — shortcuts now follow the printed key instead of the US-QWERTY physical key position.

Pull-Requests

• Fix Windows 11 high-DPI blur and QWERTZ Undo/Redo mismatch by @ortanaV2 in #1

v1.3.1-patch

Full Changelog: v1.3.0...v1.3.1

Patched

• Enforcing minimum window size for full functionality

v1.3.0

Full Changelog: v1.2.0...v1.3.0

New Features

• "Dragging Connections" setting — choose in Settings whether dragging a component/wire/selection also drags along anything attached at its endpoints ("Stay Connected", today's behavior), or leaves everything else exactly where it is ("Detach") — unplugging the connection instead of stretching it into a diagonal.
• SN74HC540N — Octal Inverting Buffer/Line Driver, 3-State — replaces CD74HC04E as the Logic Gates category's NOT gate, verified pin-for-pin against the real datasheet. The retired CD74HC04E is unaffected and still placeable under a new "Obsolete" category, so existing schematics referencing it keep working.

Improvements

• TC74HC373APF's OE pin now genuinely tri-states its outputs, matching the real chip — previously present only for correct pinout/labeling with no simulated effect. Multiple latches can now share a bus directly through their own OE, without an external tri-state buffer per latch.
• Doubled the character limit for Section labels (32 → 64) and Text Labels (48 → 96).
• Section-Label / Text-Label editing now supports Left/Right arrow-key cursor movement and Ctrl+Backspace to clear the whole field, instead of only ever appending or erasing at the end.
• Large designs render and run diagnostics noticeably faster — two per-frame calculations that used to rescan the whole circuit (the lone-connection-dot pass, and diagnostics' net lookup) are now cached O(1) lookups instead.

Fixes

• Fixed the marquee-select (rubber-band) box drifting off the grid if the camera was zoomed mid-drag.

v1.2.0

Full Changelog: v1.1.0...v1.2.0

New Features

• File > Import Schematic — load another .isonic file's full contents (components, wires, vias, sections, text labels) directly into the current schematic. It's staged as a paste: a ghost follows the cursor until you click to place it, so nothing existing is ever overwritten. Each imported wire/via's layer is intelligently remapped onto an equivalent layer in the current circuit (GND/+5V matched by role, ordinary layers matched by name, with a new layer created only if nothing matches).
• CD74HC283E — 4-Bit Binary Adder with Fast Carry — new component under a new "Arithmetic" category, verified pin-for-pin and behavior-for-behavior against the real datasheet. Multiple adders can be cascaded (carry-out to carry-in) for wider addition.

Improvements

• Raised circuit capacity limits roughly 4-8x (max components, wires, vias, junctions, sections, text labels, and the diagnostics highlight caps), so schematics at real discrete-logic-CPU scale no longer silently lose elements — this is also what fixed a bug where large selections or whole-file imports could drop wires past an old, much lower cap.

Fixes

• Fixed Wire drawing and Import placement (and plain File > Open) sometimes needing a throwaway first click before responding after a modal file dialog closed — SDL was treating that first click as just refocusing the window rather than passing it through as real input.

v1.1.0

Full Changelog: v1.0.0...v1.1.0

New Features

• Multi-select — Ctrl+click to select multiple components, wires, vias, sections, and text labels at once.
• Generalized copy/paste — copy any mix of selected elements (components, wires, vias, sections, text labels) as a single unit and paste it as one atomic operation, with a live ghost preview showing the real geometry before you place it. Wire/via layer assignment is preserved on paste.
• Label tools — Introducing Section Label and Text Label for better overview.
• Camera save/restore — pan and zoom are now saved with the schematic file and restored on load. Double-middle-click resets the camera to its default view.
• Diagnostics visibility settings — toggle the bottom-left error/warning chip stack and hover-description tooltips independently in Settings.
• Latch/state persistence — ICs that hold state purely by reading back their own outputs (e.g. the D-Latch) now correctly restore that state on save/load.

Improvements

• IC placement ghost is now a fully accurate, highlighted preview (real body/pins/notch, translucent fill, consistent valid/invalid coloring) instead of a simplified placeholder.

Fixes

• Fixed the GND/+5V plane not reaching pins or wires depending on their position in the layer stack, and not propagating through a via to a wire on an unrelated layer.
• Fixed cross-layer wire connections not splitting the touched wire into two segments (same-layer connections always did); carefully scoped so this only happens at a new wire's own start/end, never at incidental interior crossings — including on file load, which previously behaved differently from manual drawing.
• Fixed dangling vias left behind as a phantom junction after deleting one of the wires they bridged.
• Fixed newly-placed components not electrically connecting to a wire they were dropped onto.
• Fixed pins being falsely flagged as "floating" despite being connected via a mid-span wire tap.
• Fixed Section-Labeling drag-to-draw drifting off-grid if the view was zoomed mid-drag.

v1.0.0

Full Changelog: v1.0.0-preview...v1.0.0

Isonic v1.0.0

Isonic is a schematic-capture and live logic-simulation tool for building
computer architectures from wires and ICs — from single gates up to full
CPUs — with support for emulating your own real ICs, multi-layer PCB-style
routing, and direct EEPROM programming.

This is the first stable release, promoting the v1.0.0-preview build with
a round of new tooling and UI fixes.

New since the preview

• IC rotation — press R while placing an IC (Components menu or
  Ctrl+C/Ctrl+V) to rotate it 90° before dropping; rotation round-trips
  through save/load.
• Annotations — two new taskbar tools for organizing a schematic without
  affecting simulation: Section-Labeling drags out a labeled, resizable,
  lockable rectangle to frame off part of a circuit; Text Label drops a
  single freestanding line of text. Both are full Select-tool citizens
  (marquee-select, drag, delete, undo/redo, copy/paste) and save/load with
  the schematic.
• Ctrl+S to save directly, and Ctrl+V now pastes Sections/Text
  Labels too (previously components only). The Via tool's default key moved
  from V to F to stop colliding with paste.
• Manage Data panel now highlights the row for an AT28C64B's currently
  addressed byte.
• Fixed a batch of UI z-order/layering and panel-alignment bugs (diagnostic
  chips, dropdowns, wire layer draw order, panel opacity/row alignment), a
  UI-clipping bug where diagnostic chips ran invisibly underneath the
  Manage Data panel, and a taskbar layout regression from the Manage Data
  button's spacing.

v1.0.0-preview

Full Changelog: https://github.com/ortanaV2/Isonic/commits/v1.0.0-preview

Isonic's first release - a schematic-capture and live logic simulator for building digital circuits from single gates up to full CPUs, with an eye toward doubling as the schematic-entry foundation for PCB design.

Implemented

• Live logic simulation with real-time signal propagation across nets
• Multi-layer PCB-style routing — named, colored layers with GND/POWER roles, connected via vias
• Circuit diagnostics overlay — flags bus conflicts, overwritten drivers, floating pins, and fan-out overloads directly on the canvas
• Full undo/redo for structural edits, including mouse back/forward button support
• File menu — New Schematic, New Window, Open, Save, Save As, Close Window, with unsaved-changes prompts
• Custom .isonic save format — layers, components, wiring, vias, and EEPROM contents all round-trip
• Settings popup — configurable autosave interval, Layers panel corner, and fully rebindable tool/action keybinds, persisted per user
• EEPROM (AT28C64B) data editor — view and edit memory contents directly without wiring up address/data pins
• Custom IC framework — define a chip's pinout and behavior once, place it like any built-in part
• Built-in IC catalog: logic gates (AND/OR/NOT/NAND/NOR/XOR), 8:1 and dual 4:1 multiplexers, 1:8 and dual 1:4 demultiplexers, tri-state buffer, D-latch, 12-bit binary counter, 555 timer, AT28C64B EEPROM

Notes

• Windows only for now — see the README for controls and installation