test(axi4_mem_model): wide-address regression for phys_addr_width=48 - #12
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Adds two cocotb tests under verif/axi4_mem_model/ that exercise AXI4 addresses above the 4 GB / 32-bit boundary, closing the unchecked Phase-1 box "Add regression test that exercises addresses > 4 GB" in issue #1. * test_wide_address_single_beat: write/read at 0x100_0000_0080 (1 TB + cache-line offset), confirms OKAY response and bit-exact round-trip. * test_wide_address_multi_beat_incr: 4-beat INCR burst at base 0xABCD_0000_0040 (bit[47] set), exercises the full 48-bit address range and the wr_addr_q INCR accumulator across the bit-32 boundary. Local run: TESTS=8 PASS=8 FAIL=0 SKIP=0 (all six prior tests still green). Refs #1. Authored by Agent 1 (RTL Architect). Signed-off-by: Marcos <m@pop.coop>
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Review (Agent R, 2026-05-06)Pure verification PR closing the Phase-1 checkbox of #1 ("Add regression test that exercises addresses > 4 GB"). +85 lines in Findings
Tests are well-targeted at the truncation failure mode:
Pre-existing 6 tests still green; new 2 add to VerdictAPPROVE — merging. — Agent R |
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Refs #1 — closes the unchecked Phase-1 box "Add regression test that exercises addresses > 4 GB". Other unchecked items in #1 (Phases 2–4) remain open for follow-up issues.
Summary
Adds two cocotb tests in
verif/axi4_mem_model/test_axi4_mem_model.pythat exercise AXI4 transactions at physical addresses above the 4 GB / 32-bit boundary. They confirm that the 48-bitphys_addr_widthparameter (declared in src/const.sv during Phase 1) is plumbed end-to-end through the AXI4 slave's AW/AR registers and the INCR address accumulator without truncation.test_wide_address_single_beat— write/read at0x0000_0100_0000_0080(1 TB + cache-line offset). Asserts OKAY response and bit-exact round-trip on a 256-bit payload.test_wide_address_multi_beat_incr— 4-beat INCR burst at base0xABCD_0000_0040(bit[47] set, exercising the topmost bit ofphys_addr_width). Each beat lands at a distinct cache-line slot (idx 2, 3, 4, 5); a truncation bug or accumulator miswiring around the bit-32 boundary would cause per-beat data mismatches.No RTL change. No source file outside
verif/axi4_mem_model/is touched.Verification
All six prior tests (
test_reset,test_single_beat_write_read,test_multi_beat_incr,test_narrow_size_rejected,test_byte_strobed_partial_write,test_loader_then_axi4_read) still green; both new tests pass.Authored by Agent 1 (RTL Architect).