1.0.0-beta.8 Public Beta

Eighth public beta.

SPICE Model Support

• MOSFET Level 1 and Level 3, with long-channel charge-based gate charge.
• VDMOS — the vertical power MOSFET, whose card states three nodes rather than four.
• JFET — previously there was no J element at all, and one JFET took a whole subcircuit down.
• IGBT, with a closed-form Miller capacitance.
• Ferrite bead.
• P-channel MESFETs, for the three laws that have an unambiguous mirror.
• Diode, NPN and PNP — already existed.

A SPICE model file now has two doors into circuitRF. Use the new Spice component, or copy the
definition into your workspace as an editable cell. Both read the file through the same translator.

Place the file directly — the new SpiceModel component

• Drop it into schematic, double click on it, then point it at a file
• Symbol is dynamic - it depends on the contents of the Spice model
• Name lists every definition the file provides, and leaving it blank picks the highest-level
  one.
• Any parameter the chosen .subckt declares becomes an editable row, seeded at the
  definition's own default, so a part's W, L or M sweeps like anything else.

Import as a cell — model cards

File ▸ Import ▸ Model or Subcircuit… — one card becomes one cell: a schematic with the native component,
its parameters and pins already wired, and a symbol copied from that component's own artwork.

Alternatively, drag and drop Spice file into the Project Tree, then use: Project Tree ▸ Known Files ▸ Copy to Workspace as Cell…

Import as a cell — subcircuits

A .subckt becomes a cell holding the definition's own components, wired as the file wires them,
with one pin per declared port.

• The wires are drawn, not just implied. circuitRF reads a schematic's nets off the drawing.
• Grounds get their own symbols rather than a rail laid across the sheet.
• Nesting creates more cells and tells you so, all-or-nothing across every folder.
• One unreadable line refuses the whole definition. A netlist with a line missing is not a
  smaller circuit — it is a different one that elaborates, simulates and produces numbers. Refusals
  are named: a model the file does not define, a card with no circuitRF model behind it, a net count
  that disagrees with the component, a definition with no ports, a cycle.
• .sp, .spi and .cir join .subckt in the Project Tree's own list; .lib and .txt stay
  available through the picker, since those extensions name plenty of other things.

Behavioural sources

An E or G source with VALUE={…} now imports, which is what most modern library files are
made of.**

• A G source becomes an SDD port equation almost directly.
• The charge idiom — a behavioural source driving a capacitor through a midpoint node — is
  recognised and collapsed into one device stating a charge.
• .func definitions are inlined at translation time, including 102 mutually-nested ones in a
  single file, and a file's global .params become the cell's variables. TEMP resolves.
• Where a device would have converged to something unphysical, the reader refuses instead — a
  refusal is worth more than an import that throws three steps later on someone else's machine.

Library files with more than one part

• A .lib section can now be chosen, on the component and in the import picker, so a file
  offering tt / ff / ss alternatives gives you the one you asked for. Leaving it blank means
  no section, which is different from a section named "" — and a sectioned file read with no
  section chosen now says so, instead of reporting that it holds no definitions.
• A shared core no longer blocks a library's second part. Two top-level parts over common
  internals used to write the core on the first import and then refuse the second — on the core,
  not on anything you had chosen. Import is now one plan for everything you tick: a shared cell is
  written once, and the cell that opens is the first one you chose.
• Re-importing is safe and honest. A cell already imported from the same definition is reused;
  a cell you have since edited and a cell whose name now belongs to a different definition
  each get their own sentence rather than a generic name clash.
• Two files defining the same name is reported, never resolved by read order.

Unused SPICE Parameters — new documentation

Every device family already documented its own omissions. Nothing documented the layer between a
SPICE file and those devices — which card parameters are carried, which are not, and why. That is
the layer that prints "6 not carried" at you.

Reference ▸ SPICE Import is a new chapter covering both routes, the fact that the not-carried
list is exhaustive and spelled the way your card spells it, the five reasons a parameter is
dropped, why a LEVEL number is read on a MOS card and never on a MESFET card, and how to decide
whether an omission matters for your part. The list is also written onto the imported cell's own
schematic, so it survives.

Harmonic Balance: terminal currents at a capacitive port

Fixed SDD issue with current referencing to other devices for charge. ** A probe in series with a charge-carrying branch read the wrong order of magnitude, and a device's own port rows read exactly zero.** A terminal current is a sum over all of a device's weighting terms — conduction, charge, and any the device defines itself — and two consumers were reporting only the conduction term.

Data Display

• A narrowed X range now survives being saved. A trace typed as SP1.S[10..50, 1, 1] came back
  as the whole axis — and invisibly so, because the card went on showing the range you typed while
  the plot drew every point. A mid-session S/Z/Y toggle or signal reselection was throwing the
  narrowing away too.
• A trace that cannot be resolved now says <invalid> instead of ending the session. Resolving
  a trace is a read, and no read should cost an unsaved workspace. A failure also writes one line
  naming the cube, its actual shape and the slice asked for.
• Undo in a floating Data Display no longer undoes other documents not in focus.

Workspaces/Documents/Archive Improvements

• Archive Workspace now carries everything the design points at. A Touchstone file referenced
  as ../refdata/dut.s2p never travelled — the three path conventions in play (document-relative,
  workspace-relative, results-relative) were not all being tried, so the scan concluded the
  schematic referenced nothing. Invisible on the sending machine, where the path still resolves.
• A SPICE deck travels as a subtree, not a loose file. A .lib that pulls in a shared model
  file contributed one row and arrived without its contents; the recipient found out at Simulate
  time, on a different machine, from a message about a file they had never heard of. The whole
  include closure now travels with its directory structure intact, so every .include resolves
  after the copy exactly as it did before.
• Everything under results/ is ticked by default now, .npy included — the recipient of an
  archive rarely has the kit chain to re-simulate with, and a display with no data behind it renders
  nothing. Loadpull files get their own heading, and there are Include All / Include None buttons.
  A results file a document plots but you unticked is now warned about.
• Save As, then re-open the original, no longer gives you two tabs of the same document. A
  session answers to exactly one path; the old path is now unbound. The same fix covers the
  duplicate dirty-state marks that came with it.
• A saved tab and a re-opened tab now show the same title — one read 01, the other 01.csch.
• New Workspace no longer offers to restore a file from a window you closed cleanly.
• A pin whose net is labelled is now drawn connected, because it always was connected — only the
  visuals disagreed. This is how an imported subcircuit connects a terminal its router could not
  reach.
• The SnP File path resolved against the wrong base in the inline editor. For a schematic in a
  sub-folder — which is where a cell's schematic actually lives — editing File from a 2-port to a
  3-port left the symbol drawing two pins and the netlist binding two nets, silently.