1.0.0-beta.14 Public Beta

Fourteenth public beta.

Importing boards and Gerber sets

• A board import now writes the stackup rows — the copper layers, in
  order, bound to their drawing layers. You must still enter the substrate numbers (thickness, er,
  loss tangent) - what you no longer do is hand-author eleven rows to reproduce what the importer already knew.
• The board thickness the file claims is carried onto the stackup and shown beside the live sum of
  your layer thicknesses, with a disagreement marked and neither number silently corrected.
• A drill file's plating is honoured, so a non-plated mounting hole is no longer extracted as a
  barrel shorting every layer it passes through.
• A parameter file beside the artwork is now read — the coordinate format the whole job was written
  with, and the tool listing's plating column. A declaration outranks an inference; where the file
  itself disagrees, the file wins and both values are printed. One parameter file per data kind is an
  ordinary folder shape now, not a contradiction that disables both.
• A board netlist beside the artwork is read as evidence, never as geometry. It settles which holes
  are vias and which are component pins — the old guess was systematically wrong on every through-hole
  pin — and puts net names back onto composited regions, the only route back to something compositing
  destroys for good. And an archive in a folder that yields no artwork is offered rather than ignored.

The Technology Stackup tab

• Conductivity has a preset list — five metals at 20 °C — beside a field that stays freely typeable.
• A plated via's wall thickness is explained and defaulted to the 25 µm every shipped technology
  uses, so an imported board no longer fails circuitRF's own validator on a field with a known answer.
• Via entries are listed as their own group instead of as a row inside the z order, where a via
  added before the conductors appeared above the top copper. Two entries sharing a name are reported,
  and Add now numbers them. A freshly imported six-layer stackup's sixteen "not entered yet" messages
  are one summary line that shrinks as you fill it in.

Workspace History

• The Restore Points and Versions panels are now one History panel — automatic restore points and
  the versions you kept on purpose in one filtered list, at Window ▸ Panels ▸ History and on the
  workspace toolbar.
• File ▸ Clone Workspace… copies a workspace onto your machine from an address, for when a shared
  library is handed out centrally rather than sitting on a share. circuitRF asks for no sign-in and
  stores none — it uses whatever your machine's git is already set up with, and an address it cannot
  supply credentials for stops and says what was wanted rather than hanging.
• File ▸ Pull Changes now shows what came down: versions on the other copy and not on yours are
  listed at the top of the History panel, dimmed and counted, and your files change only if you pick one.
• A workspace archive now has option to include its history — one checkbox on the archive dialog, off by
  default, which gives the recipient every version and restore point. First the dialog says how much
  larger the archive gets and names the files in the history that are no longer in the workspace:
  a project archived for one customer can carry another customer's deleted artwork, with nothing in
  the visible file tree showing it.
• Settings ▸ Revision Control is now on every machine. Without a usable Git it is greyed out with
  one line saying no history is being kept anywhere and why, rather than absent — and the Git row stays
  live, because installing git and pressing Detect is the remedy.

Command Line Improvements

• circuitrf render <path> -o out.{svg,pdf,png} turns a schematic, symbol, layout or data display
  into a picture from a script, a CI job or an assistant. Every pixel comes from the code that draws
  each frame in the application, so it is the picture the window would have shown. One command over
  every kind — a cell folder takes --view, a workspace takes --cell, and a document belonging to no
  workspace renders on the fallback palette exactly as the layout editor does.
• --fit (the default), --window or --center/--span frame the view; a window of a different aspect
  is letterboxed, never cropped. On a layout every coordinate carries a unit and a bare number is
  refused — 500 could be DBU, µm or mm, and all three draw a plausible picture of the wrong thing.
• --detail full draws exactly what is stored, --detail screen uses the level-of-detail a canvas
  does — on a real board, 6.2 MB in 0.36 s against 23.5 MB in 1.44 s. --layers and --hide-layers
  narrow what is drawn.
• circuitrf explain answers the three questions you need first — --cells, --layers with
  per-layer shape counts so you do not ask for an empty one, and --extents, the box a fit frames on.

Netlists, analyses and results

• A netlist line the reader does not understand is now refused. An unknown type= is refused
  listing the legal ones, an unknown key is named with the legal keys for its analysis, and every
  missing required key is reported at once. Such a line used to be accepted, and the document then
  simulated something else.
• Unit= on a sparam directive now applies to start, stop and step, as it already did inside a
  parametric sweep. A 0.5–6 GHz sweep had been running at 0.5–6 Hz and returning a flat S11 that
  looked entirely reasonable.
• An inline unit works in a netlist assignment, as it always did in a schematic: VDS = 48 V.
• Boolean parameters read the same way everywhere. BiasTee=true, =1 and =Yes used to produce
  a Tuner with no bias tee at all.
• An instance line binding the wrong number of nets is refused before the run, naming the count. A
  short line used to skip expansion in silence and build a wired-wrong circuit that ran to completion.
• Every result cube says what its numbers are in, with "unknown" a legitimate answer for your own
  measure expression. One result had carried the same efficiency twice — a cube in percent and a scalar
  as a fraction — with nothing saying which was which.
• A two-port with a 12 Ω second port is written and read back as one: the per-port references
  travel with the file and nothing is renormalized. sparam -o honours the extension you gave it,
  and a name asking for a format it cannot write is a refusal listing the ones it can.
• explain --analysis no longer calls a chain runnable when it names a tuner the design does not
  have, and says which reference failed.

For AI assistants - MCP Improvements

• render is available to an assistant, and the result carries the rendered file itself rather than
  a path many clients cannot open.
• The component catalogue says how many nets a line binds, not how many pins the symbol draws. A
  client that wrote a one-net Tuner line from the old description got a bench whose bias tee delivered
  nothing, with every diagnostic clean, and wrote the part up as defective.
• Reference pages for analysis directives, data displays and technologies, generated from the
  readers that enforce them. And a result can be narrowed instead of returned whole — --at,
  --range, --interp, --result summary; one question about one frequency of a 551-point two-port
  run used to cost 173 kB.

Misc

• The layout Property Inspector follows the display unit. Switching µm to mil with a shape selected
  left every row showing the old unit's numbers — and committing the untouched field you could see
  would have re-read 254 µm as 254 mil.
• Arming Pin, Term or GND from the schematic toolbar now clears the selection. With a resistor
  selected, R rotated the resistor and Delete deleted it.
• Removing a cell no longer offers to save it on the way out, which would have written the file back
  and un-removed half the cell. A torn-off panel no longer outlives its window — its buttons still
  worked. Library Palette order: Vdc now sits after VProbe, and Bead and SRLC trade places.

1.0.0-beta.13 Public Beta

Thirteenth public beta.

Schematic Updates

• Added VProbe component - A voltage probe names a net and reports it, and changes nothing.
  Drop a VProbe on a net and its voltage appears in the results under the probe's own name. Delete
  every probe from a design and the answer is bit-identical. On an unnamed net the probe's name becomes
  the net's name, so you get one row you chose instead of n7.
• Placing a current probe now breaks into the wire instead of being shorted by it. The stretch between
  the two pins is removed in the same undoable placement — and only when that provably changes no
  circuit, so a junction, a crossing wire or a label in the way stops the cut.

Workspace Revision Control using Git

circuitRF now uses Git (if installed on your system) to manage and control workspace history. This
means that you can get your workspace back to a state from an hour ago, a week or month ago.

• Revision control is optional and Git must be installed for revision control to work.
• Restore points are taken for you, in 3 different ways — when you ask (File ▸ Keep
  This State…), when the workspace closes, and before an AI assistant changes anything. Not on every
  save, which would keep half of an edit that spans three files, and not on a timer.
• Versions are the ones you keep on purpose. File ▸ Keep This Version… records the whole
  workspace under a title you wrote. Automatic restore points and deliberate versions are separate
  lists in separate panels — Window ▸ Panels ▸ Restore Points and ▸ Versions — because three
  hundred automatic entries with four deliberate ones among them is a list nobody reads.
• Going back is one action. Pick an entry, and the workspace returns to how it was — with a
  restore point of what is being replaced taken first, so going back is itself undoable. Results are
  left alone. A version records which state it was brought back from, so two versions in a row where
  the second reverts the first do not read as an unexplained change of mind.
• Selecting a version lists the documents that differ from the one before it, at the granularity
  of documents rather than lines.
• An assistant cannot edit a workspace without a way back. An AI edit opens a batch first, under
  its own stated intent, and is refused outright — before anything is modified — if history is off,
  if there is nowhere to record into, or if a window is holding unsaved changes. Every refusal says
  what to do instead.
• No version history is created by merely opening a workspace to look. Opening a workspace records nothing.
• Settings ▸ Revision Control holds all the settings
• Headless too - works from the command line: circuitrf history checkpoint | list | restore | commit | versions.

Data Display

• A decibel trace now bottoms out at −250 dB. on a plot or table.
• The trace card and the trace stay on the same signal. After a post-run reload the picker could
  re-point the plot to the first signal while the card still showed your pick — the card reading
  DC1.I while the plot drew DC1.V, with nothing on screen disagreeing.
• Picofarads and nanofarads plot. Two absolute constants made small numbers unplottable: every tick
  of a picofarad axis snapped to zero, and a 100 nF trace's real variation was classified as no extent
  at all and replaced with a fixed half-farad box. Both are relative now, and one engineering formatter
  serves ticks, table cells and markers.
• Additional derived S-parameter metrics for 2-ports — |Z|, ESR, reactance, C effective, L effective and Q —
  computed under a fixture you state: shunt-through, series-through or as 1-port.

Files, workspaces and libraries

• A cell referenced from another workspace is now read-only, and the refusal opens the workspace
  that owns it and lands on the cell. Editing a library cell through a reference used to write the
  file and record the change in nobody's history.
• Five document kinds can now be removed from the Workspace Project tree — technologies,
  EM setups, harmonicaRF and wBond documents and colour themes — where the file manager was previously
  the only way. Removing a technology counts what points at it first and re-points the workspace in the same
  operation.
• Rename Workspace renames the folder and repoints every reference from the other workspaces you
  have open.
• A microstrip's parameter editor names the technology it takes H/T/Er/Sigma/TanD from, and lets
  you pick a different one.
• Command line: circuitrf check part.s2p reports the sweep, reference impedance, frequency ordering, passivity,
  reciprocity and a causality measurement; explain part.s2p reports the self-resonance and the
  impedance floor under every fixture side by side, which is the fastest way to identify an unlabelled
  file. Passivity and reciprocity are warnings carrying the measured number — an amplifier is supposed
  to have gain.

Misc

• Match's DC Block toggle is now "Shunt DC Block". Read cold, the old label said the opposite of
  what the control does: it blocks each shunt inductor that would short the supply, it does not put a
  capacitor in series with the signal. The tooltips and the reference chapter now lead with what the
  control is not.
• A background update can be relaunched into from the Messages panel. The Relaunch button quits
  through the ordinary Quit — every window still asks about unsaved work, and cancelling calls the
  whole thing off — then starts the new version and reopens the workspaces that were open.

1.0.0-beta.12 Public Beta

Twelfth public beta.

New Import Component (Symbol + Footprint) Command

• File ▸ Import ▸ Component… takes a folder, scans it, and offers a ranked list of what it
  can read. One cell comes out — symbol, footprint and the pin-to-pad map that joins them, so a symbol
  pin and the layout pad at that index are the same terminal. Density variants become layout views;
  named thermal pads survive.
• Nine formats read: .kicad_sym, .kicad_mod, .lib, .lbr, the .p/.d/.c
  triple, .hkp, .PLX/.DSL, .cxf and .scr.
• A part instance is numbered from the prefix its library states — U1, not X1.
• Pin names from an imported symbol are drawn, with a per-instance override on the context menu, and
  a name sits on the edge its pin sits on rather than straddling its own lead.
• Scanning a large folder shows progress and can be cancelled, and says when it stopped early
  instead of reporting a short list that looks like a small folder.

Improved Command Line + MCP Server Support

• Every verb answers --json. One JSON document on stdout and nothing else — results, the
  loadpull table, refusals and diagnostics included. A failed run still emits a document, so a caller
  never has to tell "no output" apart from "output I could not parse".
• Create a correct document headlessly. circuitrf new workspace <dir>, new cell <ws> <name> and
  import part <file> --into <dir>. Each calls the same code the New Workspace / New Cell / Import
  Component dialogs call, and every default is the default those dialogs open on — so what you get
  headlessly is what you would have got by clicking.
• circuitrf check <path> — is it well formed, does it resolve, is it sound? Runs no analysis and
  writes nothing, so it is safe after every edit, on a read-only tree, and on a workspace you have open
  in the app. Point it at a workspace, a cell folder or one file. Every finding comes from a validator
  the application itself uses, so a design that passes here is not refused when you open it.
• circuitrf explain <path> — what did circuitRF decide? Which technology, which layout, which
  analysis chain and for which verb, what an expression evaluates to in the design's own scope
  (--expr), and where a relative reference lands (--ref). It reports the walk as well as the
  answer, since resolution here is a series of walk-ups. A sweep is reported in base SI with its unit
  and its scale.
• circuitrf read <path> hands back a .npy, a Touchstone file or one of circuitRF's own documents
  as JSON.
• circuitrf reference serves the reference pages plus a catalogue of every netlist primitive with
  its terminals and its parameters — generated from the running build, never transcribed, so it cannot
  drift from what the engine actually accepts.
• circuitrf serve --root <dir> speaks a protocol over stdin/stdout so an external client can reach
  those verbs directly, confined to one directory. It calls the same verbs a shell does; nothing is
  reachable there that is not reachable from your terminal.
• Run verbs now refuse an option they do not read. lp x.cnl --maxmix 3 used to answer
  File not found: 3 — the dropped flag's value became the input path — and dc x.cnl --set Vg=1 ran
  silently without the override, answering a different question than the one asked.

Borrowing a cell from another project

• Referencing a cell brings in just that cell, not the entire workspace. It opens, places and
  drags like any other cell, marked with the network glyph and with its own filter toggle.
• Removing a reference really removes it, and a reference that breaks can be put back:
  Re-reference Cell… on a broken instance searches the likely places first, and one undo entry
  repairs every instance carrying that reference.
• A technology disagreement is a dialog with buttons, not prose: use theirs for this layout, for the
  whole workspace, or copy the cell in. A workspace with no technology adopts theirs with no clicks.
  Only the layers the referenced cell actually occupies are compared, so two projects sharing a metal
  stack are no longer refused over documentation layers.
• Dropping a large referenced cell no longer freezes the window — about a minute on a real library
  cell, now 32 ms — and the Add Cell dialog opens immediately rather than after the scan.
• A broken instance is findable at board extents. Its placeholder was under a pixel on a 100 mm
  board; thousands of them also went from 382 ms a frame to 15 ms.

Vias, layout and schematic editing

• Blind and buried vias export as blind and buried vias. Every writer took the pad's copper and the
  opposite outer copper, so a blind via left circuitRF as a hole drilled clean through the board,
  silently. Vias drawn in the editor also exported with no annular ring, or flashed their pad into the
  drill file.
• A blind via imports as a blind via — and an imported board's vias resolve a span at all, through
  vias included. A via stating no layer pair takes the outermost copper, which is what it means.
• The Via tool refuses a layer no via entry claims, instead of placing a via that draws perfectly and
  is inert in DRC, in EM and in every export.
• A port dragged to another face of a pad names the face it landed on — and stays clickable where it
  now is. Rotate was never at fault; the port was never being selected.
• Right-clicking empty schematic canvas offers Pop Out; there was no context menu there at all.
• Design ▸ Place Cell Instance… (Ctrl/Cmd+Shift+I) places a cell in a schematic or a layout, and the
  picker lists referenced cells too. View now sits beside Window on the menu bar.
• A symbol drawn after the cell editor was open can be made primary without restarting.

Workspaces, files and updates

• A workspace opens with its panels already in place, instead of snapping into position at the very
  end of a long open.
• The empty document area shows the Welcome icon rather than No documents open.
• Save Workspace As copies the workspace folder — cells, technologies and documents — and switches
  this window to the copy. It was an ordinary file picker writing a single file nothing looks for.
• A model file placed in an unsaved schematic stays found. Thirty seconds in, the first autosave
  silently re-based every relative reference on the recovery folder, so a SPICE model, a Touchstone file
  or a cell reference resolved into a directory nothing had been pointed at and that is deleted on exit.
• After an automatic update on macOS, workspaces under ~/Documents open. They were refused with the
  protected-folder message until you quit and launched again; the update handed over in a way that left
  the system's permission grant naming the bundle it had just replaced.
• Closing an undocked document's last tab closes its window.
• Release notes cover the versions you skipped. Updates only ever offer the newest release, so a
  machine left off while two went out never saw the middle one's notes.

Documentation

• Every component's terminal order is documented, with a note wherever the order matters — the dot
  convention on coupled inductors, a taper's two widths, the direction an I() measurement is signed
  against. A third of the library was showing net 1 is terminal 1, which is a placeholder, not a fact.

1.0.0-beta.11 Public Beta

Eleventh public beta.

Dramatic Speed Improvements for Layout Rendering of Complex Designs

Measured on a real 20-layer board — 3,284 shapes, 764,110 vertices:

• Panning that board goes from 4 fps to about 70 fps (248 ms a frame → 14 ms). Nine tenths of the frame
  was spent stroking outlines at a scale where they were not drawing edges at all — they were painting
  solid colour over every layer beneath.
• A panel of placements is dramatically faster. A 10×10 array of that board took 1,500 ms a frame,
  with a first frame of 36.7 seconds; it now runs at 1.5 ms a frame with a first frame of 72 ms.
• Clicking, or starting a marquee, in a complex design that arrays a complex cell: 1,063 ms → 0.7 ms. Every
  cell of the array was descended into and every shape inside it tested individually, so clicking
  empty canvas — the gesture that starts a marquee — was the worst case rather than the cheapest.
• The workspace window UI elements are now responsive even when large complex designs are loaded

Gerber Import Improvements

• A board that declares its unit on the same line as its coordinate format now imports. One
  %...% block may hold several commands; circuitRF read only the first, so %FSLAX45Y45*MOMM*% had
  its format read and its unit dropped — and then refused the file for declaring no unit. On the
  reported board that was twenty artwork files, twenty refusals, and only the drill data getting
  through.
• Vias are recovered from composited copper. Any board with a ground plane paints its copper in
  clear polarity, which merges each via pad into the pour around it. Via pairing looked for a discrete
  pad, found none, and imported zero vias from 1,555 holes — so the board went on to simulate with
  no vias in it. 1,475 vias are now recovered on that board; the remaining 80 are mounting and tooling
  holes with no copper pad. The pad size is the file's own aperture — nothing is invented, and the
  copper area is conserved.
• Inner copper layers are identified as copper. A set naming its layers Top Layer, Layer 2 …
  Layer 5, Bottom Layer had the four inner ones identified as nothing at all. Only conductors enter
  the stackup, so two thirds of that board never reached the EM path.
• Drill files with seven-digit millimetre coordinates read correctly instead of falling back to a
  3:3 format that put every hole ten times too far out. A rout file of routed slots and no plain hits is
  now checked against the artwork extent — it used to count zero hits, agree with itself, and skip the
  retry. A drill drawing is no longer mistaken for drill hits.
• The drill-format prompt has Apply to all and says how many files are left; a CLI --drill-*
  flag now answers it for the whole run.
• The layer-mapping dialog names the format you are importing — it said GDSII for Gerber, DXF and
  board imports alike — and its Map to column is reachable, having opened off the right-hand edge with
  horizontal scrolling disabled.
• Importing a large Gerber set shows a cancellable progress bar in the Messages panel.
• Loading a complex Gerber is now in the background and is 4× faster.
• Opening a workspace no longer sits on a blank window. Its layouts are read ahead on a background
  thread; the longest freeze over a workspace open drops from 1,256 ms to 469 ms. A progress row
  appears only if the work actually proves slow, so an ordinary open still looks exactly as it did.

Layout Editor

• A rounded rectangle has a corner-radius grip on all four corners, not just the top-left — and the
  right-hand pair now follow the cursor instead of fleeing it at twice the speed.
• Drawing tools snap to geometry, with the snap glyphs, from the moment the tool is armed. Only
  Select, Ruler, Port and Instance ever asked for geometry snapping; a drawn point landed on the grid
  even when its ghost sat on the geometry.
• A hole's centre is snappable.
• Opening the technology pane no longer changes the layout's zoom, and closing it no longer changes
  it back.
• Pasting a layout into a slide sizes the page from what is visible. A hidden layer far from your
  selection used to make the visible shape arrive too small to read.
• Change Technology lists every technology in the workspace, not just those directly in tech/ —
  which is what Browse could already reach.

Technology files

• A technology imported from a Gerber set no longer opens onto a wall of warnings, repeated on every
  load: 22 problems became 2 on the reported file, and 1 on a fresh import. Nineteen named a layer alias
  that could never have worked, and a via in a stackup with no conductors reported three unanswerable
  problems instead of the one that matters. The banner now shows the visible tab's problems, its text is
  selectable, and the Messages panel gets one line per technology rather than the whole list every time.

Verilog-A and compiled models

• Compiled Verilog-A models now run on Windows. The helper that hosts them was never built there at
  all, so every Windows installer shipped without it — and the refusal you got said you needed a C
  compiler, which was not true on the platform you were reading it on. Both Windows architectures ship,
  and the model's own build decides which is used.
• A freshly placed model no longer warns that OpVars is undeclared. It is circuitRF's own
  operating-point read-back switch, and was never sent to the model in the first place.

Updates and installers

• An update now takes effect on the launch that installs it, on Windows and Linux, instead of the
  one after it. Reverting a bad update had the same defect and the same fix. macOS was never affected.
• Linux packages carry a helper built for the architecture they target. Both the x64 and the ARM
  packages could ship the build machine's own binary — plainly present, and refusing to run.
• The About dialog names the build you are running, and its text is selectable.

1.0.0-beta.10 Public Beta

Tenth public beta.

Verilog-A Improvements

• Fully tested with ASM-HEMT and MVSG-HEMT physics-based compact models
• A Verilog-A component now accepts a .va source file directly. circuitRF compiles it by
  running a compiler you have installed, caching the result on the source's content, so an unedited
  model compiles nothing. Name your compiler under Settings ▸ Security & Permissions, or leave it
  blank to use the one on your path. Compiler errors pass through verbatim, line and column intact.
• Load Parameters… reads a fitted parameter set from a file, instead of 50–200 picker gestures
  per placed device. Names the model does not declare are reported, never dropped.
• Self-heating models now actually run. Thermal nodes were classified as electrical, and every
  terminal was reported to the model as connected, so a model that grounds its own thermal node wrote
  no equation for it and the DC solve had no solution. A model carrying its own thermal RC is no
  longer warned about on every run.
• Operating-point quantities are readable. A compiled model computes gm, gds, capacitances,
  temperature and more at every bias point, and all of it was being discarded. Now returned and
  plottable — DC1.OP("X1.gm") in a measurement, and at a large-signal point captured per sample and
  returned on the analysis' own harmonic axis, so k=0 is the cycle average. Per instance, on by
  default, with a checkbox to turn it off.

Several workspaces open at once

• File ▸ New Window and Open Workspace in New Window… give each workspace its own window,
  with its own panels, documents and undo history.

Referencing a cell in another workspace

• A design can now instance a cell that lives in another workspace, by reference, without
  copying it in. The reference names the workspace rather than spelling a path, so relocating the
  other project is one edit in the workspace file instead of a rewrite of every design.
• File ▸ Reference Workspace… creates the link; File ▸ Add Cell to Workspace…, or a
  drag from one Project Tree onto another, asks whether to copy the cell in or reference it where
  it lives. Sub-cells can follow the copy or stay referenced. Before a copy runs, the dialog says what
  will arrive, which names collide, and which kits the destination workspace does not have.
• Layouts are checked for a matching technology. Layers match by number, so an external cell's
  Drill could otherwise become your Substrate. The refusal names the layer and what it means on each
  side; two workspaces holding copies of the same technology file are no longer refused.
• Renaming or deleting a cell counts references across every open workspace, instead of
  reporting zero for a cell another project is using. Archives include the referenced cells.

Shared libraries

For the workflow where one workspace of cells lives on a network share, read-only to everyone but
the librarian.

• A library organised into folders is now browsable. A librarian who filed 200 cells into
  passives/, amplifiers/ and footprints/ published a library that rendered empty; references
  into it always resolved, only the browsing was missing.
• A read-only workspace is now recognised as one. Save is disabled with its reason in the tooltip
  rather than failing after the edit, the quit prompt offers Save As, and the document carries the same
  band a foreign document does. Editing a library cell to read it stays allowed. A layout generator
  there used to blame your parameters — the parameters were fine, the directory was not writable.
• A changed cell interface is reported, not discovered later as a dangling wire. An instance
  records the interface it was placed against; at document open, a cell whose ports have changed is
  named once per cell with the ports that are now unconnected. Accepting the new interface is one
  explicit, undoable gesture.
• Two people opening one workspace is now noticed. An advisory notice says who has it open, on
  which host and since when, and offers read-only, open anyway, or cancel — it never claims to lock
  anything.
• Editing over a VPN is faster. Resolving a referenced cell cost four filesystem round trips per
  component per edit — 160 for a forty-component schematic, on every keystroke-scale change. Those are
  now cached briefly, and the library is re-walked on open and on Refresh, not on every activation.

Moving cells

• Cells and folders can be dragged within the Project Tree — organising a workspace previously
  meant leaving the application for the file manager.
• A move repoints the references in both directions — designs elsewhere that place the moved
  cell, and the references stored inside it that point back out. A cell moved in a file manager
  broke both, silently.
• A move leaves a forwarding record, so a design in a workspace nobody has open — on a colleague's
  machine, referencing your library — still finds the cell. A file at the old path always wins over the
  record. The design says so once per moved cell, in ordinary text rather than the colour that means
  broken; adopting the new location is an explicit, undoable gesture. A move whose record cannot be
  written is refused before the move, rather than breaking references quietly.

Layout and import

• A hairline-heavy imported board is 3.6× faster to pan and zoom. A 4-up RF panel imported from
  Gerber — 77,000 shapes, its pours drawn as one-mil strokes — rendered at 456 ms a frame and now
  renders at 127 ms. Two causes: the merge tier bypassed the geometry cache entirely, and a 2-pixel
  outline on a trace 0.1 pixels wide was drawing the outline instead of the trace.
• Merging a vector-filled pour now finishes. The Gerber import tells you to merge such a layer
  into one region before setting up EM ports; on that same panel, merging ran over forty minutes
  without completing. The union now reduces as a balanced tree: 76,517 shapes across ten layers in
  9.8 s, one copper layer's 47,530 strokes collapsing to 190 polygons.

Elsewhere

• Fixed Library pallet window that refused to close
• F fits every plot in the Data Display, the gesture the schematic, symbol and layout editors
  already have. Typing an "f" into a tab name or an axis label no longer refits.
• A workspace reference can be removed from the Referenced Workspaces row, which until now needed
  a hand edit of the workspace file. Nothing is deleted in either workspace.
• Settings has its own documentation chapter, reached from a Help button in the dialog. The four
  paragraphs of standing help text on the Security tab moved onto the controls they explain as
  tooltips, so the tab now fits without scrolling.
• Help ▸ Crash Reports… opens the right folder on Windows. It depended on whether your user name
  contained a space; three other Reveal-in-file-manager surfaces had the same bug.

1.0.0-beta.9 Public Beta

Ninth public beta.

Import Gerber and Excellon files

File ▸ Import ▸ Gerber…

• A whole file set at once, or one file. The dialog offers both; folder import classifies each
  file by its contents, so a specific file extension does not matter.
• Drill files pair up with their copper. Excellon holes become vias on the layers the plated
  span names, not loose circles on a scratch layer.
• Apertures, macros, polarity and regions are honoured — a plane with clearances arrives as a
  plane with clearances, not as an outline.
• An unstated Excellon coordinate format is refused, never guessed. Leading and trailing zero
  suppression differ by four orders of magnitude on identical text, so circuitRF prints what it
  inferred and the flag that settles it, rather than handing you a board 10,000× too small.

Layout editor

• Technology ▸ Edit… now opens the technology beside your layout instead of as another tab, wide
  enough for the full layer table — so layers can be toggled with the artwork still on screen. If
  you have already torn it off or placed it yourself, that placement is kept.

Harmonic balance

• An undefined tone is now refused by name. A Tone naming a variable your design does not have
  was silently substituted with 1 GHz, and every message after that described a frequency grid
  nobody asked for — including a commensurability refusal that blamed an innocent source. The
  refusal now names the analysis, the field, the expression as you typed it and the missing
  variable. Loadpull and loadpull-pursuit carried the same fallback and are fixed with it.
• The Analysis card lists every tone in a multi-tone run. A two-tone setup showed one
  fundamental and gave no sign the second existed.

Component, Palette & Schematic

• The SDD's "+" button now offers the port equations the device can actually use, each seeded
  with a value that runs. It previously offered a slot that silently replaced your seeded equation,
  slots for ports that do not exist, and rows that were blank — which is a parse error at Run.
  V[p], C[n] and named constants were also being rejected by the name check and swallowed by the
  file reader, though the engine reads all three.
• The impedance-network "+" is gone, along with a parameter that matched no spelling the engine
  reads and was inert on every run. A Z-matrix is fixed by the port count, so there was nothing to
  add; a stray row from an older file can be deleted.
• The palette no longer offers the same part under two names — the bare Z tile placed exactly
  what Z2P places. Use Z1P / Z2P / Z3P.
• SPICE now also lists under Devices and Nonlinear. What a SPICE component references is usually
  a transistor or a diode, so it should be findable where you would shop for one.
• BiasTee and ShowBias are pickers on all three Tuner tiles, not text boxes — each takes one of
  two spellings, and a typo used to read as the default with nothing said. All three Tuner glyphs
  now render on one row.
• VAR and MEAS labels now sit against their own glyph instead of hanging down and to the left of
  it. The label anchor was sized for a two-terminal part with leads. A parameter added after you have
  moved a label block joins the block, rather than appearing alone at the un-moved default position.

Data Display

• Converting a rectangular plot to Smith or Polar now gives a square the same size as a new one.
  It kept the wider dimension, so a converted plot came out oversized (and a converted table too
  narrow). Smith/Polar swaps and adding or removing traces still keep whatever size you set.
• Complex numbers format consistently regardless of your system's regional settings.
• Continued work on the intermittent crash some of you have reported when re-simulating with
  plots open. This round cleared the last shape-based explanation by measurement and added the stack
  and full plot state to the report, plus three real fixes found on the way: two arrays that could be
  read past each other while a trace was being rebuilt, an empty reference-impedance record that now
  falls back to 50 Ω the way a missing one already did, and a zero-port network. If you can still
  reproduce it, the note it writes now contains what we need — please keep sending them.

circuitrf convert — command line layout format conversion

circuitrf convert board.kicad_pcb out.gds
circuitrf convert gerbers/ artwork.clay

• Formats are inferred from the paths — a folder is a Gerber file set, an unfamiliar extension
  is classified by its contents. --from / --to override.
• The layer mapping matches the dialog's default, so a headless conversion and one done in the
  app agree.
• Byte-for-byte identical to what File ▸ Export writes from the same design.

Windows: the application icon

Per-user installs drew generic icons everywhere — on the Start menu shortcut, on circuitRF.exe
in Explorer, and on every .cws, .csch, .cdd and .cem document. One cause, four symptoms: the
small launcher that a per-user install puts at the install root carried no icon at all, and Windows
draws a shortcut with the icon found in its target.

All three architectures now ship the icon compiled in, verified out of the built file rather than
assumed.

Documentation

• Searching the docs finds pages by their opening sentence again. 19 of 35 reference pages were
  carrying their one-line summary nowhere in the search index — searching for "bondwire" did not find
  the wBond page, whose own first line reads "Bondwire arrays".
• Reference ▸ Tuner now states which analyses the Tuner works in, what impedance it presents at
  each frequency, and that the source tuner's drive comes from the analysis's own power ladder rather
  than from any parameter on the part.
• A new CLI chapter covers convert.
• The Known Files folder in the project tree no longer shows an empty tooltip.

1.0.0-beta.8 Public Beta

Eighth public beta.

SPICE Model Support

• MOSFET Level 1 and Level 3, with long-channel charge-based gate charge.
• VDMOS — the vertical power MOSFET, whose card states three nodes rather than four.
• JFET — previously there was no J element at all, and one JFET took a whole subcircuit down.
• IGBT, with a closed-form Miller capacitance.
• Ferrite bead.
• P-channel MESFETs, for the three laws that have an unambiguous mirror.
• Diode, NPN and PNP — already existed.

A SPICE model file now has two doors into circuitRF. Use the new Spice component, or copy the
definition into your workspace as an editable cell. Both read the file through the same translator.

Place the file directly — the new SpiceModel component

• Drop it into schematic, double click on it, then point it at a file
• Symbol is dynamic - it depends on the contents of the Spice model
• Name lists every definition the file provides, and leaving it blank picks the highest-level
  one.
• Any parameter the chosen .subckt declares becomes an editable row, seeded at the
  definition's own default, so a part's W, L or M sweeps like anything else.

Import as a cell — model cards

File ▸ Import ▸ Model or Subcircuit… — one card becomes one cell: a schematic with the native component,
its parameters and pins already wired, and a symbol copied from that component's own artwork.

Alternatively, drag and drop Spice file into the Project Tree, then use: Project Tree ▸ Known Files ▸ Copy to Workspace as Cell…

Import as a cell — subcircuits

A .subckt becomes a cell holding the definition's own components, wired as the file wires them,
with one pin per declared port.

• The wires are drawn, not just implied. circuitRF reads a schematic's nets off the drawing.
• Grounds get their own symbols rather than a rail laid across the sheet.
• Nesting creates more cells and tells you so, all-or-nothing across every folder.
• One unreadable line refuses the whole definition. A netlist with a line missing is not a
  smaller circuit — it is a different one that elaborates, simulates and produces numbers. Refusals
  are named: a model the file does not define, a card with no circuitRF model behind it, a net count
  that disagrees with the component, a definition with no ports, a cycle.
• .sp, .spi and .cir join .subckt in the Project Tree's own list; .lib and .txt stay
  available through the picker, since those extensions name plenty of other things.

Behavioural sources

An E or G source with VALUE={…} now imports, which is what most modern library files are
made of.**

• A G source becomes an SDD port equation almost directly.
• The charge idiom — a behavioural source driving a capacitor through a midpoint node — is
  recognised and collapsed into one device stating a charge.
• .func definitions are inlined at translation time, including 102 mutually-nested ones in a
  single file, and a file's global .params become the cell's variables. TEMP resolves.
• Where a device would have converged to something unphysical, the reader refuses instead — a
  refusal is worth more than an import that throws three steps later on someone else's machine.

Library files with more than one part

• A .lib section can now be chosen, on the component and in the import picker, so a file
  offering tt / ff / ss alternatives gives you the one you asked for. Leaving it blank means
  no section, which is different from a section named "" — and a sectioned file read with no
  section chosen now says so, instead of reporting that it holds no definitions.
• A shared core no longer blocks a library's second part. Two top-level parts over common
  internals used to write the core on the first import and then refuse the second — on the core,
  not on anything you had chosen. Import is now one plan for everything you tick: a shared cell is
  written once, and the cell that opens is the first one you chose.
• Re-importing is safe and honest. A cell already imported from the same definition is reused;
  a cell you have since edited and a cell whose name now belongs to a different definition
  each get their own sentence rather than a generic name clash.
• Two files defining the same name is reported, never resolved by read order.

Unused SPICE Parameters — new documentation

Every device family already documented its own omissions. Nothing documented the layer between a
SPICE file and those devices — which card parameters are carried, which are not, and why. That is
the layer that prints "6 not carried" at you.

Reference ▸ SPICE Import is a new chapter covering both routes, the fact that the not-carried
list is exhaustive and spelled the way your card spells it, the five reasons a parameter is
dropped, why a LEVEL number is read on a MOS card and never on a MESFET card, and how to decide
whether an omission matters for your part. The list is also written onto the imported cell's own
schematic, so it survives.

Harmonic Balance: terminal currents at a capacitive port

Fixed SDD issue with current referencing to other devices for charge. ** A probe in series with a charge-carrying branch read the wrong order of magnitude, and a device's own port rows read exactly zero.** A terminal current is a sum over all of a device's weighting terms — conduction, charge, and any the device defines itself — and two consumers were reporting only the conduction term.

Data Display

• A narrowed X range now survives being saved. A trace typed as SP1.S[10..50, 1, 1] came back
  as the whole axis — and invisibly so, because the card went on showing the range you typed while
  the plot drew every point. A mid-session S/Z/Y toggle or signal reselection was throwing the
  narrowing away too.
• A trace that cannot be resolved now says <invalid> instead of ending the session. Resolving
  a trace is a read, and no read should cost an unsaved workspace. A failure also writes one line
  naming the cube, its actual shape and the slice asked for.
• Undo in a floating Data Display no longer undoes other documents not in focus.

Workspaces/Documents/Archive Improvements

• Archive Workspace now carries everything the design points at. A Touchstone file referenced
  as ../refdata/dut.s2p never travelled — the three path conventions in play (document-relative,
  workspace-relative, results-relative) were not all being tried, so the scan concluded the
  schematic referenced nothing. Invisible on the sending machine, where the path still resolves.
• A SPICE deck travels as a subtree, not a loose file. A .lib that pulls in a shared model
  file contributed one row and arrived without its contents; the recipient found out at Simulate
  time, on a different machine, from a message about a file they had never heard of. The whole
  include closure now travels with its directory structure intact, so every .include resolves
  after the copy exactly as it did before.
• Everything under results/ is ticked by default now, .npy included — the recipient of an
  archive rarely has the kit chain to re-simulate with, and a display with no data behind it renders
  nothing. Loadpull files get their own heading, and there are Include All / Include None buttons.
  A results file a document plots but you unticked is now warned about.
• Save As, then re-open the original, no longer gives you two tabs of the same document. A
  session answers to exactly one path; the old path is now unbound. The same fix covers the
  duplicate dirty-state marks that came with it.
• A saved tab and a re-opened tab now show the same title — one read 01, the other 01.csch.
• New Workspace no longer offers to restore a file from a window you closed cleanly.
• A pin whose net is labelled is now drawn connected, because it always was connected — only the
  visuals disagreed. This is how an imported subcircuit connects a terminal its router could not
  reach.
• The SnP File path resolved against the wrong base in the inline editor. For a schematic in a
  sub-folder — which is where a cell's schematic actually lives — editing File from a 2-port to a
  3-port left the symbol drawing two pins and the netlist binding two nets, silently.

1.0.0-beta.7 Public Beta

Seventh public beta.

This release is mostly about designing a level above the circuit — a palette of ideal system
blocks you can wire into a block diagram and simulate before any of the real parts exist — plus a
three-port ideal mixer, two new lumped parts, and a search box on every page of the documentation.

System Block Components

A new System components. Each one is placed and wired like
any other component and runs in both S-parameters and harmonic balance:

• Mixer and Differential Mixer — described below.
• Filter — five prototype families in three forms, described below.
• Amplifier — gain, return loss, one third-order intercept, an optional reverse path.
• Attenuator — a fixed pad, and the supported way to give anything a passive-intermod figure.
• Balun — single-ended to differential, with amplitude and phase imbalance.
• Circulator — forward path, reverse isolation, and a real part's finite match.
• Directional Coupler — coupling and directivity, with the through loss that follows from them.
• Duplexer — two arms off one antenna port, each with its own band.
• 90° and 180° Hybrid — an equal split with the phase relationship in the title.
• Switch and Transfer Switch — position is a parameter, not a wire you move.

Together they answer the questions a block diagram exists for: level plans, cascaded gain and
cascaded intercept (a harmonic-balance run cascades them for you instead of a spreadsheet
formula), image and spurious paths, band plans and isolation budgets, and switch-state
coverage — every position of every switch in one run, because the switch state is a swept
parameter rather than a wire you rearrange.

They are ideal by construction, and the documentation says where each one will disagree with a
real part. The circulator, coupler, hybrid, balun, switch, attenuator and amplifier hold every
number you typed at every frequency, from DC upwards. A new System Components reference page
covers the whole class — what it can answer, what it cannot, and what to reach for instead.

An Ideal Mixer

A three-port ideal mixer, placed as Mixer or as MixerD — the same component with all six of
its nets brought out as pins, for when a port's return is not ground. What comes out of the IF port
is the product of what goes into the RF and LO ports.

• You never type the multiplier constant. State a conversion gain and the LO drive it holds at —
  ConvGain = -7 dB at Plo = +7 dBm, straight off a datasheet — and circuitRF derives the rest
  from the port impedances. ConvGain is a single-sideband power gain; negative is a loss.
• Both sidebands come out. A product of two cosines is half the sum plus half the difference, so
  2 GHz against a 1.8 GHz LO puts equal power at 200 MHz and 3.8 GHz. A single-sideband result
  comes from filtering the IF, or from an image-reject network — exactly as it does in hardware.
• Conversion gain tracks LO amplitude, which is what a multiplier does and why the gain is
  quoted together with Plo. Drive the LO 3 dB harder and the conversion gain rises 3 dB. If the LO
  in your test bench is not delivering Plo, the mixer is not running at the gain you typed.
• A freshly-placed mixer is ideal. The three isolations default to 200 dB and IIP3 to 100 dBm,
  meaning none and never compresses; type a real number into any of them to turn it on. LO-to-RF,
  LO-to-IF and RF-to-IF leakage and the three port impedances are all separately settable.
• The compression law is a tanh rather than the textbook cubic. A bare cubic turns over and goes
  negative past its peak, and harmonic balance then converges cleanly onto that wrong answer.

Filter

Response picks the family — Butterworth, Chebyshev, InvChebyshev, Bessel or
Elliptic — and Form picks Lowpass, Bandpass or Highpass. A parameter the chosen family does
not read is ignored rather than refused, so changing family never means clearing a field first.

• Order is the prototype order. The bandpass transformation doubles the degree, so Order = 3
  as a bandpass is a 6th-degree network. Both conventions exist in the wild; this one is stated.
• For the three all-pole families the far stopband falls at 20 × Order dB per decade.
  InvChebyshev and Elliptic put transmission zeros on the jω axis instead, which buys their sharp
  transition and is why their stopbands level off at Astop rather than continuing to fall.
• Zin and Zout are independent, so an unequal pair makes the filter a lossless impedance
  transformer as well as a filter — matched at both ports in its passband.
• IL lays a flat loss on top and dissipates: it multiplies S21 and leaves S11 alone, the way
  a real filter's loss does.
• The Filter and the Match network share one glyph, on purpose — impedance matching is a form of
  filtering. Tell them apart by the type label and instance name.

Amplifier

• IP3Ref says whether the intercept you typed is input- or output-referred, defaulting to
  Output because that is the form a power amplifier's datasheet quotes. There is deliberately one
  field rather than two that could contradict each other.
• P1dB is not a separate knob. One nonlinearity sets compression and intermodulation together,
  so the 1 dB compression point follows from the intercept and lands at IIP3 − 8.96 dB
  input-referred — the soft limiter's own value, two-thirds of a decibel off the textbook cubic's.
• It is unilateral unless you turn S12 on. With no reverse path there is no feedback loop,
  which is what makes an ideal amplifier unconditionally stable at every frequency and every
  termination; setting S12 is what makes stability a question at all.
• Mismatching a port does not quietly re-scale the gain. A datasheet states gain and return loss
  as independent measurements, and so does this block.
• It has no supply, no bias pins, no efficiency, no PAE and no thermal node, by design. If those
  are the question, the answer is a real device model and a harmonic-balance loadpull.

Passive Intermodulation

Five blocks can carry a PIM specification — the Attenuator, the Circulator, the Directional Coupler
and both Hybrids. It is off by default, and a block stays linear at no cost in a harmonic-balance
run until you switch it on.

• It is one specification in two fields. PIM is the absolute level of the third-order product
  in dBm, and PIMPc is the power per carrier it was measured at. Both, always — a product level
  means nothing without the carriers it was measured against.
• Suppliers quote it both ways, and the conversion is product (dBm) = carrier (dBm) − product (dBc). A part specified at −153 dBc with two +43 dBm carriers is PIM = -110 dBm,
  PIMPc = 43 dBm.
• Away from PIMPc the product rides the third power of drive — 10 dB less carrier is 30 dB
  less product — which is the whole reason the carrier power travels with the specification.
• It is deterministic and memoryless, not noise-like: the same product level every run. It is
  generated on the wave incident at each port and then routed by the block's own S-matrix, so on
  a circulator the product appears where the carriers go and is suppressed at the isolated port by
  the block's own isolation.
• An attenuator with a small loss and a PIM figure is a standalone PIM generator, which is the
  supported way to give a filter, a duplexer or anything else a passive-intermod contribution.

An S-parameter run reports the port matches and the three leakages and no conversion at all — and
that is the right answer rather than a missing one. S-parameters are a single-frequency
measurement, and conversion is the business of moving energy between frequencies. Conversion gain
comes from harmonic balance: drive RF and LO as two tones and read the IF power at the product you
want. For conversion gain versus frequency, wrap that in a parametric sweep of the RF frequency.

Series and Parallel RLC Components

Two new lumped parts, SRLC and PRLC, each carrying R, L and C in one component.

• SRLC puts the three in series — the shape a real capacitor takes above a few hundred
  megahertz. A ceramic capacitor's datasheet ESR and ESL go straight into R and L. It is
  series-resonant at 1/(2π√(LC)), where its impedance falls to R: a capacitor below that
  frequency, an inductor above it.
• PRLC puts them across the same two nodes — a tank. At resonance the reactances cancel and the
  part is purely resistive at R, which makes it the natural way to enter a measured resonance.
• Their pins land exactly where a plain R, L or C's do, so you can swap one in for another
  without moving a wire.
• A Mutual may now name an L, an SRLC or a PRLC. All three carry an inductor the coupling can
  act on, and naming anything else is now reported with the kinds that do work.

Searchable Documentation

• Every page now has a search box at the right of its header, and the landing page a wide one
  between the guide cards and the prose.
• A section is the unit, not a page. Every heading with an anchor is its own record, so a result
  deep-links into a thirty-screen Reference page rather than dropping you at the top of it. 458
  records; results come back in a fraction of a millisecond.
• It works all three ways the documentation is read — over the local server the Help menu
  starts, from a web host, and by opening a page straight off disk.
• Hierarchy is now documented as a procedure. The Schematic Editor's section is six numbered
  steps, because the two things that stop people were unstated: hierarchy needs a cell, and the cell
  goes into a different sc...

1.0.0-beta.6 Public Beta

Sixth public beta.

Simulations Are Much Faster

• S-parameter sweeps run 2.5-4x faster — a Touchstone-backed part no longer re-fits its
  interpolation at every point, the matrix is rebuilt only where it actually changes, and the
  frequency grid is solved several points at a time.
• Harmonic balance runs 2-5x faster, and multi-tone gains the most — a six-tone sweep is 5x faster. Nonlinear device equations are evaluated across the whole time grid at once, which is 10-38x faster on its own.
• Loadpull benefits twice over, since every point on its grid is an HB solve, and a 640-point
  sweep now takes a third of the working memory it did.

Harmonic Balance Converges Where It Used To Give Up

The solver no longer takes a full Newton step that makes things worse — it backs off and tries a
smaller one. A drive-level sweep that returned six non-converged points now returns none, at a third
of the time per point. Drive Stepping now does something: when a cold solve is hard, the drive is
walked up in steps to the level you asked for.

Technology Editor

• A 4-layer FR-4 starter joins the 2-layer one in New Workspace — signal / ground / signal /
  ground on 62 mil, with each signal layer paired to its own plane.
• File > Save is no longer greyed out on an edited technology file. Cmd+S always worked; only the
  menu was stale.
• A via row no longer offers a Thickness field. Nothing read it anyway— the barrel's length is its span
  — and every shipped file carried zero there, which read as something you had forgotten to fill in.
• Ground-reference messages now name the planes they found and say what the cost is, instead of
  claiming no plane is marked when one is.

Project Tree

• Double-clicking a Known File opens it. A bookmarked schematic, symbol or layout used to do
  nothing at all.
• Copy to Workspace as Cell... on a bookmarked schematic, symbol or layout builds a cell in your
  workspace around a copy of it, leaving the original reference alone.
• A file inside the workspace is now listed only once, where it lives. Import Data and a file drop onto the
  tree were both producing a second copy under Known Files.
• Reveal on a broken reference now walks up to the nearest folder that still exists and says so.

Data Display

• Max Gain is plotted correctly now. MAG/MSG is a power gain, so its dB is 10log10 — it was being
  computed and labelled as a 20log10 quantity, reading 2x too large in dB. The trace card now offers
  a real linear / dB10 choice rather than a unit annotation, and marker readouts and the axis label
  agree with it.
• Derived traces survive a re-run. Max Gain and the stability circles used to vanish from a
  display whenever the S-parameter analysis was re-run, and were then dropped when the file was
  reopened. Ordinary S(i,j) traces were never affected, which is why it looked so arbitrary.
• Run (Cmd+R) works while the Analyses panel has focus. Clicking into the panel used to grey out
  the menu item and the shortcut while the panel's own Run button stayed live.

Schematic Editor Improvements - Wires Keep Their Shape When You Move a Part

Dragging a component used to re-route every attached wire as a bare L between its two ends. That is a
re-wire, not a re-draw: anything tapping the middle of that wire was silently disconnected, and
the circuit still simulated. It also moved runs off their rows, turned horizontal wires vertical, and
occasionally laid a new leg exactly on top of an unrelated wire.

Now a moved endpoint deforms only its own end of the wire. Bends, rows and columns survive, and so
does every tap. When there is no slack, an elbow appears at the moved end — the vertical jog you would
expect under a part nudged off its row. A tap that genuinely leaves its wire grows a short stub at a
right angle instead of dragging the whole run after it, and that stub undoes with the move.

MIM Capacitors in the EM Solver

Thin-film capacitors are now expressible and simulable in the planar EM engine.

• A via drawn as a region — a plate connection, a backside slot, a bar — is now recognised as a
  via. Previously only the point via shape was, and drawn artwork on a via layer was silently
  ignored with a note saying the layer was unbound.
• A conductor entry can now say which surface of its band its analysis sheet sits on. On a MIM
  stack that is the difference between modelling a 0.2 um plate gap and a 3.2 um one.
• A capacitor dielectric is patterned with its plate, not smeared across the whole design. That
  removes the reason there were ever two GaAs technologies: mmic-GaAs_2LM_100um now carries the MIM
  module, and a run that uses only the interconnect metals is unaffected by it. Existing workspaces
  hold their own copy of the technology and are untouched.
• A port on upper metal now de-embeds. Three separate refusals used to fence off exactly the
  case a MIM run produces — a feed arriving above the substrate — and they are gone.
• The EM setup warns when the mesh is too coarse for the plate spacing, and tells you the cell
  count that would fix it rather than pointing at a setting that cannot.
• Importing a process stack now names conductors that no via reaches and drawing layers the
  stackup never binds, so an omitted optional module is visible instead of silent.

1.0.0-beta.5 Public Beta

Fifth public beta.

Significant Match Designer Improvements

• now supports lowpass & highpass (and pre-existing bandpass)
• now supports dual-band and tri-band synthesis

Electromagnetic MoM Solver

• now solves ~10x faster with ~2.4x reduction in memory use

New Components

• added BJT, ITone, and Voltage Controlled Current Source (VCCS)

Loadpull Display

• Loadpull contour markers now read out all contours on the plot

---

Details

The Match Designer

A Match is no longer only a bandpass ladder. Two new forms join it — lowpass and
highpass — each a ladder of single elements matched between F1 and F2, with the impedance ratio
pinned by the ladder's own transparency at DC (lowpass) or at infinity (highpass). Order keeps its
meaning and the element count is 2n in every form. Chebyshev and Butterworth only: once the ratio is
pinned the family has one free parameter left, so neither a second prescribed Q nor a delay target
exists for these forms. Form is an additive field defaulting to Bandpass, so a design written before
this release rebuilds the identical ladder.

Multi-band matching. The Designer now synthesises dual-band networks via a frequency mapping
and tri-band networks via a multi-interval Remez fit, both feeding the existing prototype and
element-extraction path — so a multi-band solution flattens to a cell, plots and simulates exactly
like a single-band one. Odd element counts are synthesisable too: an odd extraction terminates on a
conductance ratio. Butterworth has no tri-band member, structurally, and the Designer says so rather
than searching for one.

New feasibility hints show the per-band Fano ceiling and the gap rise beside the finished
solution list, so an unreachable specification is visible before the search runs rather than after
it fails.

A Match can carry a DC block. The Designer's DC Block toggle puts a capacitor in series with the
first real shunt inductor on each termination's DC path — found by walking the ladder rather than by
looking at the end node, so a pi of inductors gets both its hosts and an interior collision becomes
interior rather than impossible. The series inductance is compensated so the arm's reactance is exact
at f0 and second order elsewhere; the status line and the flattened record both name the route.

Four of the design note's own claims did not survive measurement, and the code follows the
measurement rather than the note. The orientation of a lowpass or highpass ladder is not free:
the family depends on the terminations only through Γ₀², which is invariant under r and 1/r, so one
extraction serves both and the low-impedance port always takes the series element. A shunt
capacitance on the low side of a step-up is therefore absorbable by neither new form. The general
numerical route cannot solve this family past order 4 — 144 cells of a 360-cell sweep fail, every
order-6 cell among them — so the roots are written down rather than searched for, taking it to zero
failures. And the near-end element is unimodal in K rather than monotone, so the search scans before
it bisects.

The Match Designer's UI, rebuilt around the Solutions list

Clicking a solution card applies it. Arrow keys step between cards and yield to a selected
marker, and applying no longer scrolls the list out from under you.

More room to see the solutions. Band and Ripple merge into one card, Probe moves onto its
termination's heading, the Specification pane sizes itself, and all the freed height goes to the
Solutions list. The filter gains a Form group above Orders, and every card names its form. Undo
and Redo sit on the title strip.

A termination edit or a probe now always lands on a solution that meets the target when one
exists, drawn from the filtered list, with candidates widening past the design's own family,
nearest first. Two bugs had been stopping that: a refused design still reported itself as on-target,
and the request was being spent on the first cell to land, which is the empty one.

Solution cards are selectable text, return loss is quoted signed, group delay carries its unit,
and the Match symbol draws its own design. A pi/T switch no longer re-frames the schematic.

The two Chebyshev families are renamed single-match and double-match — the broadband-matching
literature's own terms for one prescribed reactive termination against two. Display only; nothing in
a saved file changes.

Match fixes

• Every undo added an entry. A two-way-bound slider wrote back mid-undo, so redo was wiped and
  eight edits could take fourteen undos. A coercing control's write-back is not an edit.
• One gesture is one undo entry again. Edits are now held against the analysis landings, which
  can write the design mid-edit.
• Flatten to Cell wrote 15 significant digits into the flattened element values.
• The synthesis refusal was rendered three times.
• The solution search's generation guard was check-then-lock, so a stale search could land over
  a newer one.
• A lowpass or highpass ladder has no Norton pairs — every like-kind element in one shares an
  orientation — and the transform rack now says so with a note rather than the refusal wording,
  because that design is finished, not stuck.
• The Ripple row's note was putting a scroll bar on the specification column whenever both
  terminations carry a reactance, which is most designs; it moves to the row's tooltip.

EM simulation: about 10x faster, on layouts that used to be refused

If you run the EM simulator, this is the release you will feel. Twelve milestones of work on the
planar method-of-moments engine landed together. Here is what changes on screen.

Your sweeps finish in a fraction of the time. A frequency point on a mid-sized board that took
just over a minute now takes a handful of seconds — roughly 10x end to end. A sweep you used to
start and walk away from is now something you wait through.

Bigger layouts fit in the same machine. Memory per point dropped about 2.4x, so the same 1 GB
that used to cap you at roughly 4,450 unknowns now carries about 6,970 — half again as much
structure at the same mesh, or the same structure at a finer one.

Turn the accelerated solver on for everyday parts, not just big ones. It used to be a loser below
roughly 3,700 unknowns, so for most real parts it was the wrong choice. It now pays from about
1,100 unknowns up, and at 3,700 it is around 13x faster than the dense solve. If you have been
leaving it off out of habit, turn it on.

Runs that used to be refused by the MoM solver are now accepted. Three kinds in particular:

• Layouts with ground vias or more than one metal level can use the accelerated solver at all now.
  Previously they were forced onto the dense path and hit its ceiling. At 15,000 unknowns this is
  about 15x less memory than dense.
• De-embedded runs with wide ports. The reference-impedance step was always solved densely no
  matter what your settings said, so a wide port could refuse a run whose actual structure would have
  solved comfortably. One such run that refused outright now finishes 3 points in 107 s.
• Refined meshes that used to stall. A mesh ladder that climbed from 21 to 143 to 372 solver
  iterations and then failed to converge now runs 21 → 28 → 36.

The messages tell you the truth. Refusals used to quote about a quarter of the memory a run really
needed, so "this will not fit" arrived with a number that made no sense. A via-bearing mesh could also
pass the estimate you read before pressing Simulate and then be refused by the run itself. Both are
fixed, and the run-start message now names the solver kernel it actually resolved to instead of
hedging, reports adaptive sampling as an outcome — with a reason when it disagrees with your setting —
and no longer claims a modelled remainder on a sweep where every point was solved.

One piece of practical advice, from measuring the default. With adaptive frequency sampling on,
asking for more frequency points is close to free, and asking for fewer buys you almost nothing.
The saving comes from skipping points the engine can already predict, and the panel's default
101-point grid is not dense enough for there to be many. The same structure at 401 points solves
only 81 of them in 3.01 s, against 4.25 s for a non-adaptive 101-point sweep of the same band — four
times the resolution, in less time. So raise the point count; you will get a smoother curve for less
wall clock than you are spending today. (This also corrects the documentation, which promised a 5–10x
reduction in solve count at the default settings. On the default grid it is 1.0–1.7x. The 5–10x is
real, but you have to ask for the finer grid to collect it.)

Nothing about your existing setups needs to change to get any of this, and no result moves: the
accuracy gates on this work are exactness against the old arithmetic, not a tolerance. The engineering
detail is at the bottom of these notes.

Three new components

• BJT — a charge-control bipolar transistor intrinsic model, both polarities (BJT_NPN /
  BJT_PNP): transport currents with Early effect and high-level injection, junction and diffusion
  charge, and Rb/Re/Rc on internal nodes with base-resistance modulation. Two palette tiles, one law.
• ITone (I_1Tone / I_nTone) — a current excitation, the dual of VTone: the same tone
  table, the same DC offset and the same multi-tone behaviour, with I/Idc where VTone has V/Vdc. The
  shared machinery is a common base type, so a current tone source cannot slip past a
  commensurability check or a sweep-point re-evaluation.
• VCCS — an ideal voltage-controlled current source, four terminals in two ...