Multi-tile configuration of CachePool

[DiyouS]

Overview

This PR introduces the multi-tile configuration of the CachePool cluster, extending the architecture from a single-tile design to a scalable multi-tile system. The default configuration is updated to 4 tiles with 16 cores total.

Features

Group Hierarchy

A new Group level is introduced between the Tile and Cluster, containing a configurable number of Tiles connected via a crossbar. This enables scaling the core count and cache capacity beyond a single tile while keeping inter-tile communication latency bounded.

Peripheral Reorganization

Memory-mapped registers and peripherals (including the bootrom) are moved out of the Spatz cluster and fully into CachePool at the cluster level. This centralizes control and simplifies the per-tile design. A new register is added to configure the private cache partition start address.

Two-Level Hardware Barrier

A two-level hardware barrier replaces the previous single-level barrier to support global synchronization across all tiles in a group. The first level synchronizes cores within a tile; the second level synchronizes across tiles.

Cache Bank Partitioning

The L1 cache banks can now be partitioned at runtime between a shared pool (accessible cluster-wide via the interconnect) and a private partition (local to each tile). Three configurations are currently supported, with more planned:

• All-shared: all banks contribute to the cluster-wide interleaved cache pool
• All-private: all banks are local to the tile, not visible to remote tiles
• Half-private / half-shared: half the banks are private, half remain in the shared pool

Partitioning is controlled via a memory-mapped register (l1d_private). The interconnect (tcdm_cache_interco) uses a runtime-configurable address rotation scheme to present a dense index space to each cache bank regardless of partition mode, preserving full SRAM utilization. The refill unit applies the inverse rotation before issuing misses to the NoC.