timing annotated netlist simulation and dynamic poser estimate using OpenSTA

[jeras]

Hi, I would like to run a timing annotated netlist simulation so I could use the resulting VCD containing toggling information to run a dynamic power estimation using OpenSTA. I do not need a perfect annotation for now, but I would like to see some glitches due to signal races.

For now I am still stuck at SDF annotation. Do you know of any examples I could use as reference, either using IHP130 or a different open source PDK?

A bit more about my current progress:

1. I modified 05_finishing.tcl to get a SDF file. Questa (the latest bundled with Altera tools is version 2025.3) expects the separator / while the CVC simulator expects the separator ..
2. I created a new top level testbench tb_croc_chip which instantiates the entire CROC chip (croc_chip including IO pads), and updated the compile_tech.tcl to include missing IO pads, ... Since CVC is probably unable to compile much SV code, the testbench can be run without JTAG VIP code (for now I should see the boot ROM sequence).
3. I modified bender and vsim scripts to be able to run a timing annotated netlist simulation. I also created a CVC script, which does not use bender.

Status with Questa:

I got Questa to process the SDF file with some errors which I silenced. But there were not delays in the simulation and when I tried to debug the issue by dumping the simulators internal data using TCL command write timing --recursive /tb_croc_chip/i_croc_chip/, it appears not delays were actually applied.

Status with VCV:

I get a lot of warning, the problematic ones seem to be:

** WARN** [679] specify paths in top level module sg13g2_dfrbp_1 ignored - should be in library
** WARN** [679] specify paths in top level module sg13g2_dfrbp_2 ignored - should be in library

and then I get the error:

**../openroad/out/croc.sdf(5105) ERROR** [1366] hierarchical port name reference i_croc_soc\/i_croc\/gen_sram_bank\[0\]\.i_sram\/gen_512x32xBx1\.i_cut.A_ADDR[0] illegal Verilog name

I got here using $sdf_annotate, I was unable to get the CVC command line argument +sdf_annotate [file]+[scope reference] to accept a scope reference (maybe I should escape separators?).

I will try to remove the offending lines from the SDF file and try again.