Add CLIC support

[niwis]

Add a CLIC to the Ariane system and make the necessary changes to the core. We follow the RISC-V "Smclic" and "Ssclic" extension specification:
https://github.com/riscv/riscv-fast-interrupt/blob/master/clic.adoc#clic-csrs

System:

• Add CLIC as submodule (or bender dependency) (non-funcional)
• Instantiate CLIC in ariane_testharness and ariane_xilinx
• Switch to new uniform setup for CLIC and CLINT mode: CLINT connects to CLIC and core (we do not need the generate block in the soc anymore)

Interface:

• Add kill and kill_ack signals to allow swapping pending interrupt. kill_ack is asserted if the current interrupt has not been accepted yet. Otherwise, the pending interrupt will be regularly acknowledged (ack), and the kill request becomes obsolete.
  • CVA6
  • CLIC
• Propagate privilege mode of interrupt
  • CVA6
  • CLIC
• Change irq to ID encoding
• Optional pack CLIC <-> CVA6 interface signals into struct for cleaner code

Core:

• Update interfaces in a backwards-compatible way (non-funcional)
• decoder: Insert interrupts in processor pipeline
  • m-mode
  • s-mode
• Acknowledge taken interrupts
  • Implemented
  • Double-check
• Add runtime switch between CLIC and non-CLIC modes
• Aggregate CLIC logic in stand-alone module
• Purge additions if CLIC is compile-time disabled

M-Mode CSRs:

• Update mstatus
• Update medeleg/ mideleg
• Update mie/mip
• New CLIC mode in mtvec
  Note: In CLIC mode and shv=1, the core jumps to mtvt + id instead of M[mtvt + id]!
• Add mtvt
• Update mcause
• Add mnxti (optional)
• Add mintstatus
• Add mintthresh
• Add mclicbase

S-Mode CSRs:

• Update sstatus
• Update sedeleg/ sideleg
• Update sie/sip
• New CLIC mode in stvec
• Add stvt
• Update scause
• Add snxti (optional)
• Add sintstatus
• Add sintthresh

Verification:
Extend riscv-tests here => pulp-platform/riscv-tests#2

• VERIFY
• Simple smclic tests
  • Implemented
  • Integrated into CI
• Simple ssclic tests
• Boot Linux