Implement single-cycle RV64I core

[ranaumarnadeem]

Summary

First milestone of the RV64IMAC+Zicsr roadmap: a real, verified single-cycle RV64I core, built on this branch's simpler single-module architecture rather than main's pipeline.

• Fixes real bugs in the reused alu.sv/register_file.sv/decoder.sv: SLT/SRA signedness, unmasked shift amounts, inverted regfile write-enable, x0 never hardwired, missing sign-extension on every immediate type (including a 12-vs-13-bit zero-pad bug specific to S-type store offsets), and SLLI/SRLI/SRAI reading garbage shift amounts instead of the actual shift field.
• Widens alu.sv/register_file.sv/decoder.sv to WORD_SIZE=64 and adds the RV64I-only instructions: LWU/LD/SD and the *W/*IW word-arithmetic family.
• Adds two new purpose-built memory modules, imem.sv/dmem.sv — combinational reads with real byte-enable writes, since the existing Wishbone-attached wb4_sram.sv is registered (minimum 2-cycle transaction) and can't support single-cycle timing. Real Wishbone integration is a later milestone, not this one.
• design/core.sv is a full rewrite: a genuine single-cycle datapath (no FSM) — fetch, decode, execute, memory, and writeback all complete within one clock edge-to-edge cycle.

Out of scope here (later milestones): M/A/C extensions, Zicsr/CSRs, privilege modes, Sv39, UART, JTAG, pipelining, out-of-order.

Test plan

• alu_tb.sv (11 checks) and register_file_tb.sv (6 checks) — unit-level, isolated from the core
• core_alu_ops_tb.sv (7), core_upper_imm_tb.sv (3), core_load_store_tb.sv (4), core_branch_jump_tb.sv (7), core_rv64_word_ops_tb.sv (6) — integration, each targeting a specific regression rather than just "does it run" (negative immediates, the SLT/SRA fixes, the S-type offset bug via an independent load-path cross-check, JALR's LSB-clear, ADDW/SRAW vs their 64-bit equivalents on identical inputs)
• 44/44 checks passing under iverilog (WSL)
• verilator --lint-only -Wall clean (zero warnings) across the full design

🤖 Generated with Claude Code

[bitglitcher]

Approving base RV64I architecture