This project revolves around creating a boolean logic simulator that replicates the behavior of complex logic circuits with multiple gates, input & output signals, and operations such as AND, OR, NOT, NAND, and XOR.
- 02/19/2024: Team meeting --> introductions, roles, and set tentative timeline for project
- 02/20/2024: Completed project plan
- 02/28/2024: Completed Software Requirements Specification (SRS) outline
- 03/04/2024: Team meeting --> discussed SRS document and reviewed it with team
- 03/18/2024: Team meeting --> discussed SRS document and reviewed feedback from Project Management Plan
- 03/19/2024: Updated SRS document with use case diagram
- 03/20/2024: Started programming the Boolean Logic Simulator
- 03/23/2024: Updated Project Plan --> added two teams that will work on different components of simulator
- 03/25/2024: Team meeting --> discussed SRS document progress and roadblocks
- 04/01/2024: Team meeting --> reviewed feedback of SRS document and reviewed Software Architecture Document
| Name | Role | Availability |
|---|---|---|
| Kevinh Nguyen | Team Leader / Team 1 member | Monday-Sunday: 9am - 9pm |
| Changwen Gong | Technical Leader / Team 2 member | Monday-Sunday: 9am - 9pm |
| Rajkunwar Kaura | Product Owner / Team 1 member | Monday-Sunday: 9am - 9pm |
| Riley England | Quality Assurance / Team 2 member | Monday-Sunday: 9am - 9pm |
| Kemar Wilson | Project Team Leader 1 | Monday-Sunday: 9am - 9pm |
| Abdulahi Mohamed | Project Team Leader 2 | Monday-Friday: 9am - 9pm |