Release 0.10

What's Changed

• issue #401 - First round of changes to improve clarity of document. Removed mention of U-mode interrupts. by James Ball (@james-ball-qualcomm) in #403
• Make some reorganizations in the chapter. by jb-brelot-nxp in #404
• Improved clarity regarding xcause when switching between CLIC and CLINT by Christian Herber (@christian-herber-nxp) in #408
• issue #411 - Clarify that smclicshv ignores 1 or 2 LSBs of vector table entry (depending on IALIGN) by James Ball (@james-ball-qualcomm) in #417
• James ball clic issue 411 by Christian Herber (@christian-herber-nxp) in #423
• 414 move register layout definitions into wavedrom by Bill Traynor (@wmat) in #431

New Contributors

• James Ball (@james-ball-qualcomm) made their first contribution in #403
• jb-brelot-nxp made their first contribution in #404
• Christian Herber (@christian-herber-nxp) made their first contribution in #408
• Bill Traynor (@wmat) made their first contribution in #431

Full Changelog: https://github.com/riscv/riscv-fast-interrupt/commits/v0.10