silicon-bridge

SNN-to-FPGA deployment pipeline: Q8.8 parameter export, .mem generation, and UART spike readback

---

The Rust-side bridge between trained SNN parameters and FPGA hardware. Exports weights and thresholds as Q8.8 fixed-point .mem files for Vivado/Quartus $readmemh, and provides an async UART bridge for sending stimuli and reading back spike states at runtime.

Features

• Export traits for hardware alignment with silicon-hdl:
  • FixedPointEncode — f32 → Q8.8 (u16)
  • ParameterExport — build the FPGA parameter bundle
  • MemFileWriter — write $readmemh .mem files
• FpgaParameterExporter — default implementation of those traits
• format_q88_hex / q88_to_f32 — Q8.8 helpers
• FpgaBridge — UART protocol for host–FPGA spike exchange (uart feature)
• FpgaMetrics — Vivado timing report parser (WNS for CI/CD gating; LUT field reserved / not parsed yet)

Installation

silicon-bridge = "0.1"

Quick Start

Export Parameters

use silicon_bridge::{FpgaParameterExporter, ParameterExport};

let mut exporter = FpgaParameterExporter::new();
exporter.set_thresholds(vec![0.6; 16]);
exporter.set_weights(vec![vec![0.5; 16]; 16]);
exporter.set_decay_rates(vec![0.9; 16]);

let params = ParameterExport::export(&exporter);
// → params.thresholds, .weights, .decay_rates are Vec<u16> (Q8.8 format)
// → ready for silicon-hdl WeightRam / NeuronParamRam via Vivado $readmemh

UART Spike Readback

use silicon_bridge::FpgaBridge;

let mut bridge = FpgaBridge::new()?;
let stimuli = vec![0.1; 16];
let (_potentials, spikes) = bridge.process_stimuli(&stimuli)?;

Q8.8 Fixed-Point Format

Q8.8:  value = raw_u16 / 256.0
       raw   = clamp(value × 256, 0, 65535) truncated to u16
Range: [0, 255.996]  (unsigned)
       [-128, 127.996]  (signed, two's complement)

Directly loadable by silicon-hdl WeightRam.sv and NeuronParamRam.sv (Limen-Neural/silicon-hdl).

Repo boundaries

See docs/boundary-matrix.md for what this crate owns versus neuromod, brainstem-daemon, limbic-critic, and silicon-hdl.

Extracted from Production

Extracted from Eagle-Lander, a private neuromorphic GPU supervisor. The FPGA export pipeline was decoupled from the private training orchestrator so it works with any SNN framework.

Related Ecosystem

Library	Purpose
silicon-hdl	SystemVerilog core, bridge, and SoC for Basys3 / Artix-7
SynapticDistill.jl	Julia training + distillation (Q8.8 export path)
neuromod	SNN dynamics / core runtime traits

License

Licensed under either of MIT or Apache-2.0 at your option.