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silicon-bridge

SNN-to-FPGA deployment pipeline: Q8.8 export, .mem generation, UART spike readback, Vivado WNS parsing.

Version: 0.1.0 | Edition: 2024 | License: MIT OR Apache-2.0

Host-side bridge between trained SNN floats and silicon-hdl FPGA hardware. Not a simulator, training loop, or RTL library.

Features

Area	Capability
Export traits	FixedPointEncode, ParameterExport, MemFileWriter
Default exporter	FpgaParameterExporter → Q8.8 u16 + .mem + JSON metadata
Helpers	format_q88_hex, q88_to_f32
UART (uart feature)	FpgaBridge SiliconBridge v3.0 stimuli/spikes
Metrics	FpgaMetrics — WNS from Vivado timing summary

Start Here

Page	Description
Getting Started	Install, export, UART
Project Structure	Modules and features
Architecture	Placement in the stack
Q8.8 Format	Fixed-point encoding
Parameter Export	Traits and exporter
Mem Files	Vivado $readmemh layout
UART Bridge	Protocol and ports
FPGA Metrics	Timing report parsing
Boundary Matrix	Owns vs siblings
Testing	Unit tests
CI and Quality	GHA
Ecosystem	Related repos
Glossary	Terms

Quick export

use silicon_bridge::{FpgaParameterExporter, ParameterExport};

let mut exporter = FpgaParameterExporter::new();
exporter.set_thresholds(vec![0.6; 16]);
exporter.set_weights(vec![vec![0.5; 16]; 16]);
exporter.set_decay_rates(vec![0.9; 16]);
let params = ParameterExport::export(&exporter);

License

Dual-licensed under MIT or Apache-2.0 at your option.

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Last updated: July 29, 2026 Updated by: Grok Build: Grok 4.5 Package tip reference: de069cd (main, through PR #18)