UART Bridge

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Generated with Grok Build: Grok 4.5 · xAI Imagine (/imagine)

Feature: uart. Module: src/fpga_bridge.rs. Depends on serialport.

SiliconBridge v3.0 (16 neurons)

Direction	Layout
TX	`0xAA` + 32 bytes (16 × Q8.8 signed stimuli as `i16` big-endian)
RX	32 bytes potentials (16 × `i16` BE Q8.8) + 2 bytes spike flags + 2 bytes switches

Stimuli: pad/truncate to 16 channels; clamp each to [-127.99, 127.99] before encode.

Spike flags: 16-bit word, bit i = neuron i spiked. Switches currently unused by the API.

Item	Role
`FpgaBridge::new()`	Open first of `/dev/ttyUSB0..2` at 115200, 100 ms timeout
`process_stimuli(&[f32])`	Round-trip potentials + spikes
`ping()`	Test stimuli; deactivates on failure
`is_active()`	Connection flag
`find_fpga_ports()`	Filter available ports containing `ttyUSB`

Linux-oriented port discovery. CI does not require serial hardware; keep feature-gated.