Project Structure

Project Structure

silicon-bridge/
├── src/
│   ├── lib.rs              # re-exports
│   ├── fpga_export.rs      # Q8.8 + .mem + traits
│   ├── fpga_metrics.rs     # Vivado WNS parse
│   └── fpga_bridge.rs      # UART (feature uart)
├── docs/
│   ├── boundary-matrix.md  # excluded from crate package
│   └── logo.png
├── .github/workflows/ci.yml
├── Cargo.toml
└── AGENTS.md / REVIEW.md

Features

Feature	Default	Effect
(none)	yes	Export + metrics
uart	off	FpgaBridge, find_fpga_ports via serialport

Dependencies

Crate	Role
serde / serde_json	Parameter metadata JSON
chrono	Export timestamps
serialport	Optional UART

No domain or neuromod simulation stacks.

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Last updated: July 29, 2026 Updated by: Grok Build: Grok 4.5 Package tip reference: de069cd (main)