Architecture

Architecture

Generated with Grok Build: Grok 4.5 · xAI Imagine (/imagine)

Canonical detail: docs/boundary-matrix.md (LIM-9).

Stack placement

Rust training / runtime crates
        │  floats, thresholds, weights
        ▼
  silicon-bridge   ── .mem / UART ──►  silicon-hdl (this repo / bitstream)
        (host)                            (FPGA)

Layer	Example
Host bridge	silicon-bridge
Hardware	silicon-hdl
Neuron models (SW)	neuromod
Sensory	axon-encoder

Historical name Spikenaut-Hardware ≈ this monorepo; prefer silicon-hdl in new docs.

Owns

• SNN FPGA primitives (LIF, RAMs, STDP controller)
• On-chip UART + SiliconBridge transport RTL
• AER SynapseRouter + thin Basys 3 tops
• Vivado/Verilator flows for this tree
• WNS gate scripts in-repo
• Dedup / ownership map

Does not own

• Rust runtime / training / reward shapers
• Host UART client / Q8.8 export tools (silicon-bridge)
• Domain adapters (trading, mining, …)
• Full multi-byte host protocol FSMs beyond byte pipe (layered above RTL)

Internal compile order

lib_bridge → lib_core → lib_soc / lib_synapse

Related

• Ecosystem
• Bridge Library

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Last updated: July 29, 2026 Updated by: Grok Build: Grok 4.5 Package tip reference: 363bd74 (main) Cubic wiki outline: page-home