FPGA Platform
Generated with Grok Build: Grok 4.5 · xAI Imagine (/imagine)
| Item | Value |
|---|---|
| Part |
xc7a35tcpg236-1 (Artix-7) |
| Clock | 100 MHz on-board oscillator (SoC top) |
| UART | 115200 baud default (matches silicon-bridge) |
| Constraints | constraints/basys3.xdc |
| Alt constraints | constraints/artix7_trainer.xdc |
SoC top keeps XDC-friendly rst_n port naming; BTNC/CPU_RESET is active-high on the board and inverted in RTL to active-low rst for submodules (documented in top header).
Last updated: July 29, 2026
Updated by: Grok Build: Grok 4.5
Package tip reference: 363bd74 (main)
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