Bridge Library

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Raul Montoya Cardenas edited this page Jul 29, 2026 · 2 revisions

Bridge Library (lib_bridge)

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Path: spikenaut-bridge-sv/rtl/
Host contract: docs/interface-alignment.md

Modules

`UartRx` / `UartTx`

Parameterized CLK_FREQ, BAUD_RATE (default 100 MHz / 115200), DATA_WIDTH (default 8). RX uses 2FF synchronizer on the async pin.

`SiliconBridge`

Wraps RX+TX for a UART byte pipe:

Defaults match silicon-bridge host serial settings.
No opcodes / sync bytes / multi-byte frames in this module.
Host “SiliconBridge v3.0” framing (0xAA + Q8.8 words + spike bitmap) is an application protocol layered in SoC FSM + host crate.

Internal ports: rx_data/rx_valid, tx_data/tx_send/tx_busy.

Related

Last updated: July 29, 2026 Updated by: Grok Build: Grok 4.5 Package tip reference: 363bd74 (main) Cubic wiki outline: page-home