Core Library

Core Library (lib_core)

Generated with Grok Build: Grok 4.5 · xAI Imagine (/imagine)

Path: spikenaut-core-sv/rtl/

Modules

LifNeuron

Leaky integrate-and-fire (parameterized DATA_WIDTH / PARAM_WIDTH, must be equal). Ports: spike_in, weight, threshold, leak, spike_out. Active-low reset; single-cycle spike pulse.

WeightRam

Single-port sync weight RAM (ADDR_WIDTH, DATA_WIDTH, optional INIT_FILE string). Block RAM style. $readmemh when INIT_FILE ≠ "NONE".

NeuronParamRam

Per-address parameter RAM (one value per addr — separate instances for threshold vs leak). Same optional INIT_FILE pattern.

StdpController

On-chip STDP with pre/post traces; drives weight write-back (weight_we only on actual change, not every spike).

Testbenches

spikenaut-core-sv/tb/ — unit TBs including INIT_FILE tests (tb_WeightRam_init, tb_NeuronParamRam_init).

Related

• Memory Init
• SoC and Demos

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Last updated: July 29, 2026 Updated by: Grok Build: Grok 4.5 Package tip reference: 363bd74 (main) Cubic wiki outline: page-home