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silicon-hdl

Deduplicated, Vivado-ready SystemVerilog monorepo for neuromorphic / SNN FPGA primitives.

Target: Digilent Basys 3 (Artix-7 xc7a35tcpg236-1) | License: MIT OR Apache-2.0

Canonical RTL for LIF + weight/param RAMs + STDP, on-chip UART bridge, thin board tops, AER router demo, Verilator/Vivado tooling, and a Deduplication Guardian. Host export/UART client lives in silicon-bridge — not here.

Libraries

Lib	Path	Contents
lib_core	spikenaut-core-sv/	LifNeuron, WeightRam, NeuronParamRam, StdpController
lib_bridge	spikenaut-bridge-sv/	UartRx, UartTx, SiliconBridge
lib_soc	spikenaut-soc-sv/	spikenaut_soc_basys3_top only
lib_synapse	synapse-link-hdl/	SynapseRouter + synapse_demo_basys3_top

Compile order: bridge → core → soc / synapse. No duplicate module definitions (guardian-enforced).

Start Here

Page	Description
Overview	Mission + Cubic map
Getting Started	Sim / Vivado
Repository Layout	Tree
Architecture	Layer boundary
FPGA Platform	Basys 3
Core Library	lib_core modules
Bridge Library	UART / SiliconBridge
SoC and Demos	Tops
Synapse Link	AER router
Memory Init	Q8.8 $readmemh
Build and Simulation	TCL / Verilator
Deduplication Guardian	Dupe radar
CI and Quality	Workflows
Ecosystem	Host stack
Glossary	Terms

Quick commands

# Vivado (from repo root)
vivado -mode batch -source scripts/build_soc.tcl
vivado -mode batch -source scripts/sim_core.tcl

# Dedup
python scripts/dedup_guardian.py

License

Dual-licensed under MIT or Apache-2.0 at your option.

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Last updated: July 29, 2026 Updated by: Grok Build: Grok 4.5 Package tip reference: 363bd74 (main) Cubic wiki outline: page-home