Overview

Overview

Wiki map for Limen-Neural/silicon-hdl, grounded in package main @ 363bd74.

Cubic wiki (topology):
https://www.cubic.dev/wiki/Limen-Neural/silicon-hdl?page=page-home

One-line mission

FPGA / SystemVerilog home for SNN primitives, on-chip UART transport, and Basys 3 tops — single-source modules, free-runner Verilator CI, optional Vivado.

Learning-field note

README positions this tree as a practice ground on the HDL curve (AI-assisted, iterative). Expect sharp edges; corrections welcome.

Cubic → GitHub page map

Cubic themes	GitHub wiki
Home / layout / agents / issues	Home, Overview, Repository Layout
HW arch / Basys 3	Architecture, FPGA Platform
lib_core / bridge / soc / synapse	Core, Bridge, SoC, Synapse Link
LIF / RAMs / STDP / UART / bridge / router	Core / Bridge / Synapse pages
AER / compile rules / dedup	Architecture, Deduplication Guardian
Verilator / TB / Vivado / CI / XDC	Build and Simulation, CI, FPGA Platform
Adding modules / demos	Repository Layout, SoC and Demos

Recent mainline

Change	Notes
#51 / #52	INIT_FILE $readmemh for RAMs + SoC merged_v2 wiring
#36	Interface alignment with silicon-bridge
#35	Boundary matrix (LIM-9)

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Last updated: July 29, 2026 Updated by: Grok Build: Grok 4.5 Package tip reference: 363bd74 (main) Cubic wiki outline: page-home