Repository Layout

Repository Layout

Generated with Grok Build: Grok 4.5 · xAI Imagine (/imagine)

silicon-hdl/
├── spikenaut-core-sv/       # lib_core
│   ├── rtl/                 # LifNeuron, WeightRam, NeuronParamRam, StdpController
│   ├── tb/                  # unit testbenches (+ INIT tests)
│   ├── mem/                 # Q8.8 .mem images (merged_v2_*)
│   └── doc/
├── spikenaut-bridge-sv/     # lib_bridge
│   ├── rtl/                 # UartRx, UartTx, SiliconBridge
│   └── tb/
├── spikenaut-soc-sv/        # lib_soc — wrappers only
│   ├── rtl/Basys3_Top.sv    # module spikenaut_soc_basys3_top
│   ├── tb/
│   └── ip/
├── synapse-link-hdl/        # lib_synapse
│   ├── src/SynapseRouter.sv
│   └── examples/basys3/     # synapse_demo_basys3_top
├── constraints/             # basys3.xdc, artix7_trainer.xdc
├── scripts/                 # build_soc.tcl, sim_core.tcl, dedup_guardian.py, …
├── tests/                   # pytest (guardian)
├── docs/                    # boundary-matrix, interface-alignment, …
└── .github/workflows/

Module ownership (exactly one definition each)

Module	Path
LifNeuron	spikenaut-core-sv/rtl/
WeightRam	spikenaut-core-sv/rtl/
NeuronParamRam	spikenaut-core-sv/rtl/
StdpController	spikenaut-core-sv/rtl/
UartRx / UartTx / SiliconBridge	spikenaut-bridge-sv/rtl/
SynapseRouter	synapse-link-hdl/src/
spikenaut_soc_basys3_top	spikenaut-soc-sv/rtl/Basys3_Top.sv
synapse_demo_basys3_top	synapse-link-hdl/examples/basys3/Basys3_Top.sv

SoC/demo instantiate core/bridge; they do not redefine them.

Related

• Deduplication Guardian

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Last updated: July 29, 2026 Updated by: Grok Build: Grok 4.5 Package tip reference: 363bd74 (main) Cubic wiki outline: page-home