3.Implementation
Table shows the
| Signals | Source | Description |
|---|---|---|
| pclk | Clock source | Clock. The rising edge of PCLK times all transferon the APB. |
| preset_n | System bus equivalent | Reset. The APB reset signal is active low. This signal is normally connected directly to the system bus reset signal |
| paddr | APB bridge | Address. This is the APB address bus.It can be up to 32 bits wide and is a data access or an instruction access. |
| pprot | APB bridge | Protection type. This signal indicates the normal, privileged, or secure protection level of the transaction and whether the transaction is a data access or an instruction access. |
| pselx | APB bridge | Select. The APB bridge unit generates this signal to each peripheral bus slave. It indicates that the slave device is selected and that a data transfer is required. There is a pselx signal for each slave. |
| penable | APB bridge | Enable. This signal indicates the second and subsequent cycle of an APB transfer. |
| pwrite | APB bridge | Direction. This signal indicates an APB write access when HIGH and an APB read access when LOW. |
| pwdata | APB bridge | Write data. This bus is driven by the peripheralbus bridge unit during the write cycle when pwrite is HIGH. This bus can be up to 32 bits wide. |
| pstrb | APB bridge | Write strobes. This signal indicates when byte lanes to update during a write transfer. There is one write strobe for each eight bits of the write data bus. Therefore, pstrb[n] corresponds to pwdata[(8n+7):(8n)]. Write strobes must not be active during a read transfer. |
| pready | Slave interface | Ready. The Slave uses this signal to extend an APB transfer. prdata Slave interface Read Data.The selected slave drives this bus during read cycles when pwrite is LOW. This bus can be up to 32-bits wide. |
| pslverr | Slave interface | This signal indicates a transfer failure. APB peripherals are not required to support the pslverr pin. This is true for both existing and new APB peripheral designs. Where a peripheral does not include this PIN then the appropriate input to the APB bridge is tied LOW. |
Hdl top is synthesizable, where generation of the clock and reset is done. Instantiation of the apb interface handle, master agent bfm handle and slave agent bfm handle is done as shown in Figure .
Fig HDL Top
Importing the global packages Passing Signals: pclk, preset_n Declaration of signals: paddr, pwrite, pwdata, pstrb, penable, pready, prdata, pslverr, pprot are declared as logic type.
Instantiates the below two interfaces here
a) apb master driver bfm and
b) apb master monitor bfm.
Instantiates the apb master assertions and binds it with the apb master monitor bfm handle and maps the signals of apb master assertions with the apb interface signals. The apb interface signals are passed to the apb master driver and monitor bfm in instantiations.
Fig. APB driver bfm instantiation in apb master agent bfm code snippet
Above Fig. are the code snippets of instantiations of apb master driver and monitor bfm
Fig. APB monitor bfm instantiation in apb master agent bfm code snippet
Apb master driver bfm is an interface where it will get the signals from the apb interface. It has a method drive_to_bfm which will be called by the apb master driver proxy which drives the paddr and pwdata data to the apb interface. fig.3.2 gives the reference of the instantiation of apb master driver bfm.
Apb master monitor bfm is an interface where it will get the signals from the apb interface. It has a method sample_data which will be called by the apb master monitor proxy which samples the paddr, pselx, pwdata and apb_avip_architectural_documentprdata data from the apb interface. After sampling the data, the apb master monitor bfm interface sends the data to the apb master monitor proxy using the output port of sample_data task. fig.3.3 gives the reference of the instantiation of apb master monitor bfm.
Instantiates the below two interfaces here
1.apb slave driver bfm and
2.apb slave monitor bfm.
Instantiates the apb slave assertions and binds it with the apb slave monitor bfm handle and maps the signals of apb slave assertions with the apb interface signals. The apb interface signals are passed to the apb slave driver and monitor bfm in instantiations
Fig APB slave driver bfm instantiation in apb slave agent bfm code snippet
Fig APB slave monitor bfm instantiation in apb slave agent bfm code snippet
APB slave driver bfm is an interface where it will get the signals from the apb interface. It has a method drive_to_bfm which will be called by the apb slave driver proxy which drives the prdata data to the apb interface. fig.3.4 gives the reference for the instantiation of apb slave driver bfm.
APB slave monitor bfm is an interface where it will get the signals from the apb interface. It has a method sample_data which will be called by the apb slave monitor proxy which samples the pwdata and prdata from the apb interface. After sampling the data, the apb slave monitor bfm interface sends the data to the apb slave monitor proxy using the output port of sample_data task. fig.3.5 gives the reference for the instantiation of apb slave monitor bfm.
Fig HVL Top
In top test is running by using the run_test(“test_name”) method, which will start the whole tb components.
Environment has the below components a. apb_scoreboard b. apb_virtual_sequencer c. apb_master_agent d. apb_slave_agent In the build phase, env_cfg handle will be called and create the memory for the above declared components. In the connect phase, the apb_master_monitor_proxy is connected to apb_scoreboard and apb_slave_monitor_proxy to apb_scoreboard using analysis port and analysis fifo as shown in fig
A scoreboard is a verification component that contains checkers and verifies the functionality of a design. The scoreboard is implemented by extending uvm_ scoreboard.
The purpose of the scoreboard in the APB-AVIP project is to
1.Compare the PWDATA, PADDR, PWRITE and
PRDATA data from the slave and master
2.Keep track of pass and failure rates identified in the comparison process
3.Report comparison success/failures result at the end of the simulation
The scoreboard consists of two analysis fifo’s which receive the packets from the analysis port of the monitor class. fig. 3.7 shows the connection between the analysis port and analysis fifo.