6.Verification Plan
Verification plan is an important step in Verification flow; it defines the plan of an entire project and verifies the different scenarios to achieve the test plan.
A Verification plan defines what needs to be verified in Design under test(DUT) and then drives the verification strategy. As an example, the verification plan may define the features that a system has and these may get translated into the coverage metrics that are set.
Bits of transfers (8, 16, 24, maximum bits 32)
Four lanes of PSTRB
- LANE 0
- LANE 1
- LANE 2
- LANE 3
Wait state & No wait state
For more information of Verification Plan click below link: APB-Verification Plan In the below Figure, Section A represents the Sl.No Section B represents the Scenarios Section C represents the Features Section D represents the Description Section E represents the Test Cases names Section F represents the Status
Fig. 6.3.1 Verification plan template
These directed tests provide explicit stimulus to the design inputs, run the design in simulation, and check the behavior of the design against expected results. No of bits transfers - This tests describes the different combinations of number of bits transfer
Table 6.4.1. Checking coverage closure for No of bits transfers
| S.NO | No of bit transfers | Test names | Description |
|---|---|---|---|
| 1 | 8bit | apb_8b_write_test | Checking the 8 bit transfer |
| 2 | 16bit | apb_16b_write_test | Checking the 16bit transfer |
| 3 | 24bit | apb_24b_write_test | Checking the 24bit transfer |
| 4 | 32bit | apb_32b_write_test | Checking the 32 bit transfers |